mainboard/gigabyte/ga-b75m-d3v: Use tabs for indents
Change-Id: I36011719f79da4a9ab2aaeb92ffb0506b4373143 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16816 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -37,36 +37,36 @@ static void mainboard_init(device_t dev)
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RCBA32(0x38c8) = 0x00002005;
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RCBA32(0x38c4) = 0x00802005;
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RCBA32(0x38c0) = 0x00000007;
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RCBA32(0x2240) = 0x00330e71;
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RCBA32(0x2244) = 0x003f0eb1;
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RCBA32(0x2248) = 0x002102cd;
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RCBA32(0x224c) = 0x00f60000;
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RCBA32(0x2250) = 0x00020000;
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RCBA32(0x2254) = 0x00e3004c;
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RCBA32(0x2258) = 0x00e20bef;
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RCBA32(0x2260) = 0x003304ed;
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RCBA32(0x2278) = 0x001107c1;
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RCBA32(0x227c) = 0x001d07e9;
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RCBA32(0x2280) = 0x00e20000;
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RCBA32(0x2284) = 0x00ee0000;
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RCBA32(0x2288) = 0x005b05d3;
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RCBA32(0x2318) = 0x04b8ff2e;
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RCBA32(0x231c) = 0x03930f2e;
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RCBA32(0x3808) = 0x005044a3;
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RCBA32(0x3810) = 0x52410000;
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RCBA32(0x3814) = 0x0000008a;
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RCBA32(0x3818) = 0x00000006;
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RCBA32(0x381c) = 0x0000072e;
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RCBA32(0x3820) = 0x0000000a;
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RCBA32(0x3824) = 0x00000123;
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RCBA32(0x3828) = 0x00000009;
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RCBA32(0x382c) = 0x00000001;
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RCBA32(0x3834) = 0x0000061a;
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RCBA32(0x3838) = 0x00000003;
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RCBA32(0x383c) = 0x00000a76;
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RCBA32(0x3840) = 0x00000004;
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RCBA32(0x3844) = 0x0000e5e4;
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RCBA32(0x3848) = 0x0000000e;
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RCBA32(0x2240) = 0x00330e71;
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RCBA32(0x2244) = 0x003f0eb1;
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RCBA32(0x2248) = 0x002102cd;
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RCBA32(0x224c) = 0x00f60000;
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RCBA32(0x2250) = 0x00020000;
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RCBA32(0x2254) = 0x00e3004c;
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RCBA32(0x2258) = 0x00e20bef;
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RCBA32(0x2260) = 0x003304ed;
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RCBA32(0x2278) = 0x001107c1;
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RCBA32(0x227c) = 0x001d07e9;
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RCBA32(0x2280) = 0x00e20000;
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RCBA32(0x2284) = 0x00ee0000;
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RCBA32(0x2288) = 0x005b05d3;
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RCBA32(0x2318) = 0x04b8ff2e;
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RCBA32(0x231c) = 0x03930f2e;
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RCBA32(0x3808) = 0x005044a3;
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RCBA32(0x3810) = 0x52410000;
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RCBA32(0x3814) = 0x0000008a;
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RCBA32(0x3818) = 0x00000006;
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RCBA32(0x381c) = 0x0000072e;
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RCBA32(0x3820) = 0x0000000a;
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RCBA32(0x3824) = 0x00000123;
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RCBA32(0x3828) = 0x00000009;
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RCBA32(0x382c) = 0x00000001;
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RCBA32(0x3834) = 0x0000061a;
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RCBA32(0x3838) = 0x00000003;
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RCBA32(0x383c) = 0x00000a76;
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RCBA32(0x3840) = 0x00000004;
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RCBA32(0x3844) = 0x0000e5e4;
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RCBA32(0x3848) = 0x0000000e;
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}
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// mainboard_enable is executed as first thing after
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@ -82,10 +82,10 @@ void pch_enable_lpc(void)
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pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
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CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
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pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
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pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
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/* Initialize SuperIO */
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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@ -93,27 +93,27 @@ void pch_enable_lpc(void)
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 5, 0 },
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{ 1, 5, 0 },
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{ 1, 5, 1 },
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{ 1, 5, 1 },
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{ 1, 5, 2 },
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{ 1, 5, 2 },
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{ 1, 5, 3 },
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{ 1, 5, 3 },
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{ 1, 5, 4 },
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{ 1, 5, 4 },
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{ 1, 5, 6 },
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{ 1, 5, 5 },
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{ 1, 5, 5 },
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{ 1, 5, 6 },
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{ 1, 5, 0 },
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{ 1, 5, 0 },
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{ 1, 5, 1 },
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{ 1, 5, 1 },
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{ 1, 5, 2 },
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{ 1, 5, 2 },
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{ 1, 5, 3 },
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{ 1, 5, 3 },
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{ 1, 5, 4 },
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{ 1, 5, 4 },
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{ 1, 5, 6 },
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{ 1, 5, 5 },
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{ 1, 5, 5 },
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{ 1, 5, 6 },
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};
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void mainboard_get_spd(spd_raw_data *spd) {
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read_spd (&spd[0], 0x50);
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read_spd (&spd[1], 0x51);
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read_spd (&spd[2], 0x52);
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read_spd (&spd[3], 0x53);
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read_spd (&spd[0], 0x50);
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read_spd (&spd[1], 0x51);
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read_spd (&spd[2], 0x52);
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read_spd (&spd[3], 0x53);
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}
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void mainboard_early_init(int s3resume) {
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