amd/pi/hudson: Add GPIO get function
Add a basic GPIO get function. Note that GPIO set, ACPI/GPE, and other features should come in future commits. Future changes to be modeled on the other soc/ gpio functions. Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19159 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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Marc Jones
Marc Jones
parent
4aad421e81
commit
dae95f0dfe
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@ -39,6 +39,7 @@ ramstage-y += hda.c
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ramstage-y += pci.c
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ramstage-y += pcie.c
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ramstage-y += sd.c
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += gpio.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
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ramstage-y += reset.c
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include "gpio.h"
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int gpio_get(gpio_t gpio_num)
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{
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uint32_t reg;
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reg = read32((void*)(uintptr_t)gpio_num);
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return !!(reg & GPIO_PIN_STS);
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}
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@ -0,0 +1,133 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _HUDSON_GPIO_H_
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#define _HUDSON_GPIO_H_
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#include <southbridge/amd/common/amd_defs.h>
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#include <types.h>
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#define CROS_GPIO_DEVICE_NAME "AmdKern"
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#define GPIO_PIN_STS (1 << 16)
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#define GPIO_OUTPUT_VALUE (1 << 22)
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#define GPIO_OUTPUT_ENABLE (1 << 23)
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
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/* GPIO_0 - GPIO_62 */
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#define GPIO_BANK0_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1500)
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#define GPIO_0 (GPIO_BANK0_CONTROL + 0x00)
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#define GPIO_1 (GPIO_BANK0_CONTROL + 0x04)
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#define GPIO_2 (GPIO_BANK0_CONTROL + 0x08)
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#define GPIO_3 (GPIO_BANK0_CONTROL + 0x0C)
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#define GPIO_4 (GPIO_BANK0_CONTROL + 0x10)
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#define GPIO_5 (GPIO_BANK0_CONTROL + 0x14)
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#define GPIO_6 (GPIO_BANK0_CONTROL + 0x18)
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#define GPIO_7 (GPIO_BANK0_CONTROL + 0x1C)
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#define GPIO_8 (GPIO_BANK0_CONTROL + 0x20)
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#define GPIO_9 (GPIO_BANK0_CONTROL + 0x24)
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#define GPIO_10 (GPIO_BANK0_CONTROL + 0x28)
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#define GPIO_11 (GPIO_BANK0_CONTROL + 0x2C)
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#define GPIO_12 (GPIO_BANK0_CONTROL + 0x30)
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#define GPIO_13 (GPIO_BANK0_CONTROL + 0x34)
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#define GPIO_14 (GPIO_BANK0_CONTROL + 0x38)
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#define GPIO_15 (GPIO_BANK0_CONTROL + 0x3C)
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#define GPIO_16 (GPIO_BANK0_CONTROL + 0x40)
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#define GPIO_17 (GPIO_BANK0_CONTROL + 0x44)
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#define GPIO_18 (GPIO_BANK0_CONTROL + 0x48)
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#define GPIO_19 (GPIO_BANK0_CONTROL + 0x4C)
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#define GPIO_20 (GPIO_BANK0_CONTROL + 0x50)
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#define GPIO_21 (GPIO_BANK0_CONTROL + 0x54)
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#define GPIO_22 (GPIO_BANK0_CONTROL + 0x58)
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#define GPIO_23 (GPIO_BANK0_CONTROL + 0x5C)
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#define GPIO_24 (GPIO_BANK0_CONTROL + 0x60)
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#define GPIO_25 (GPIO_BANK0_CONTROL + 0x64)
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#define GPIO_26 (GPIO_BANK0_CONTROL + 0x68)
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#define GPIO_39 (GPIO_BANK0_CONTROL + 0x9C)
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#define GPIO_42 (GPIO_BANK0_CONTROL + 0xA8)
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/* GPIO_64 - GPIO_127 */
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#define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600)
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#define GPIO_64 (GPIO_BANK1_CONTROL + 0x00)
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#define GPIO_65 (GPIO_BANK1_CONTROL + 0x04)
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#define GPIO_66 (GPIO_BANK1_CONTROL + 0x08)
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#define GPIO_67 (GPIO_BANK1_CONTROL + 0x0C)
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#define GPIO_68 (GPIO_BANK1_CONTROL + 0x10)
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#define GPIO_69 (GPIO_BANK1_CONTROL + 0x14)
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#define GPIO_70 (GPIO_BANK1_CONTROL + 0x18)
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#define GPIO_71 (GPIO_BANK1_CONTROL + 0x1C)
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#define GPIO_72 (GPIO_BANK1_CONTROL + 0x20)
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#define GPIO_74 (GPIO_BANK1_CONTROL + 0x28)
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#define GPIO_75 (GPIO_BANK1_CONTROL + 0x2C)
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#define GPIO_76 (GPIO_BANK1_CONTROL + 0x30)
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#define GPIO_84 (GPIO_BANK1_CONTROL + 0x50)
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#define GPIO_85 (GPIO_BANK1_CONTROL + 0x54)
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#define GPIO_86 (GPIO_BANK1_CONTROL + 0x58)
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#define GPIO_87 (GPIO_BANK1_CONTROL + 0x5C)
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#define GPIO_88 (GPIO_BANK1_CONTROL + 0x60)
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#define GPIO_89 (GPIO_BANK1_CONTROL + 0x64)
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#define GPIO_90 (GPIO_BANK1_CONTROL + 0x68)
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#define GPIO_91 (GPIO_BANK1_CONTROL + 0x6C)
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#define GPIO_92 (GPIO_BANK1_CONTROL + 0x70)
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#define GPIO_93 (GPIO_BANK1_CONTROL + 0x74)
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#define GPIO_95 (GPIO_BANK1_CONTROL + 0x7C)
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#define GPIO_96 (GPIO_BANK1_CONTROL + 0x80)
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#define GPIO_97 (GPIO_BANK1_CONTROL + 0x84)
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#define GPIO_98 (GPIO_BANK1_CONTROL + 0x88)
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#define GPIO_99 (GPIO_BANK1_CONTROL + 0x8C)
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#define GPIO_100 (GPIO_BANK1_CONTROL + 0x90)
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#define GPIO_101 (GPIO_BANK1_CONTROL + 0x94)
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#define GPIO_102 (GPIO_BANK1_CONTROL + 0x98)
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#define GPIO_113 (GPIO_BANK1_CONTROL + 0xC4)
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#define GPIO_114 (GPIO_BANK1_CONTROL + 0xC8)
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#define GPIO_115 (GPIO_BANK1_CONTROL + 0xCC)
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#define GPIO_116 (GPIO_BANK1_CONTROL + 0xD0)
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#define GPIO_117 (GPIO_BANK1_CONTROL + 0xD4)
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#define GPIO_118 (GPIO_BANK1_CONTROL + 0xD8)
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#define GPIO_119 (GPIO_BANK1_CONTROL + 0xDC)
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#define GPIO_120 (GPIO_BANK1_CONTROL + 0xE0)
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#define GPIO_121 (GPIO_BANK1_CONTROL + 0xE4)
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#define GPIO_122 (GPIO_BANK1_CONTROL + 0xE8)
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#define GPIO_126 (GPIO_BANK1_CONTROL + 0xF8)
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/* GPIO_128 - GPIO_183 */
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#define GPIO_BANK2_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1700)
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#define GPIO_129 (GPIO_BANK2_CONTROL + 0x04)
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#define GPIO_130 (GPIO_BANK2_CONTROL + 0x08)
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#define GPIO_131 (GPIO_BANK2_CONTROL + 0x0C)
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#define GPIO_132 (GPIO_BANK2_CONTROL + 0x10)
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#define GPIO_133 (GPIO_BANK2_CONTROL + 0x14)
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#define GPIO_134 (GPIO_BANK2_CONTROL + 0x18)
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#define GPIO_135 (GPIO_BANK2_CONTROL + 0x1C)
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#define GPIO_136 (GPIO_BANK2_CONTROL + 0x20)
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#define GPIO_137 (GPIO_BANK2_CONTROL + 0x24)
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#define GPIO_138 (GPIO_BANK2_CONTROL + 0x28)
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#define GPIO_139 (GPIO_BANK2_CONTROL + 0x2C)
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#define GPIO_140 (GPIO_BANK2_CONTROL + 0x30)
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#define GPIO_141 (GPIO_BANK2_CONTROL + 0x34)
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#define GPIO_142 (GPIO_BANK2_CONTROL + 0x38)
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#define GPIO_143 (GPIO_BANK2_CONTROL + 0x3C)
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#define GPIO_144 (GPIO_BANK2_CONTROL + 0x40)
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#define GPIO_145 (GPIO_BANK2_CONTROL + 0x44)
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#define GPIO_146 (GPIO_BANK2_CONTROL + 0x48)
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#define GPIO_147 (GPIO_BANK2_CONTROL + 0x4C)
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#define GPIO_148 (GPIO_BANK2_CONTROL + 0x50)
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#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) */
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typedef uint32_t gpio_t;
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int gpio_get(gpio_t gpio_num);
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#endif /* _HUDSON_GPIO_H_ */
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