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According to AMD documentation, cache type WP should be used for 

execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-02-10 20:49:56 +00:00
parent 20ecc5af40
commit daecb1888e
1 changed files with 2 additions and 2 deletions
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4
src/cpu/amd/car/cache_as_ram.inc
View File

@ -294,11 +294,11 @@ clear_fixed_var_mtrr_out:
xorl %edx, %edx
/*
* IMPORTANT: The two lines below can _not_ be written like this:
* movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
* movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $REAL_XIP_ROM_BASE, %eax
orl $MTRR_TYPE_WRBACK, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx