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soc/qualcomm/ipq40xx: Map OCIMEM 

DDR binary runs from here

BUG=chrome-os-partner:49249
TEST=Boots and DDR seems to be usable
BRANCH=none

Change-Id: I6111dddcabf05e5cb84ee9ebcc1803addb1e91cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7baf2079845964a150f51d558b396a1a9b0dc0a3
Original-Change-Id: I1d7230b229db3abfb73e6d8f9ca085650e6abec8
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333313
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14671
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Varadarajan Narayanan 2015-11-16 13:22:02 +05:30 committed by Patrick Georgi
parent a86a1837d2
commit db0c3b3192
2 changed files with 9 additions and 0 deletions
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7
src/mainboard/google/gale/mmu.c
View File

@ -20,6 +20,9 @@
#define WIFI_IMEM_1_START ((uintptr_t)_wifi_imem_1 / KiB)
#define WIFI_IMEM_1_END ((uintptr_t)_ewifi_imem_1 / KiB)
#define OC_IMEM_START ((uintptr_t)_oc_imem / KiB)
#define OC_IMEM_END ((uintptr_t)_eoc_imem / KiB)
#define DRAM_START ((uintptr_t)_dram / MiB)
#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
#define DRAM_END (DRAM_START + DRAM_SIZE)
@ -61,6 +64,10 @@ void setup_mmu(enum dram_state dram)
WIFI_IMEM_1_END - WIFI_IMEM_1_START,
DCACHE_WRITEBACK);
mmu_config_range_kb(OC_IMEM_START,
OC_IMEM_END - OC_IMEM_START,
DCACHE_WRITEBACK);
/* Map DRAM memory */
setup_dram_mappings(dram);

2
src/mainboard/google/gale/mmu.h
View File

@ -16,6 +16,8 @@ extern u8 _wifi_imem_0[]; /* Linker script supplied */
extern u8 _ewifi_imem_0[];
extern u8 _wifi_imem_1[];
extern u8 _ewifi_imem_1[];
extern u8 _oc_imem[];
extern u8 _eoc_imem[];
enum dram_state {
DRAM_INITIALIZED = 0,