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mb/mainboard/google/sarien/variants: Set correct tcc_offset value 

Set new tcc_offset value to 10 degree C. This configures the Thermal
Control Circuit (TCC) activation value to 90 degree C. It prevents
any abrupt thermal shutdown while running heavy workload. This helps
to take early thermal throttling action when CPU temperature goes
above 90 degree C.

Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Sumeet Pawnikar 2019-04-04 06:55:19 +05:30 committed by Patrick Georgi
parent a2b7be7496
commit db3ba1bc18
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -161,7 +161,7 @@ chip soc/intel/cannonlake
#| I2C4 | H1 TPM | #| I2C4 | H1 TPM |
#+-------------------+---------------------------+ #+-------------------+---------------------------+
register "tcc_offset" = "5" register "tcc_offset" = "10"
register "common_soc_config" = "{ register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -158,7 +158,7 @@ chip soc/intel/cannonlake
#| I2C4 | H1 TPM | #| I2C4 | H1 TPM |
#+-------------------+---------------------------+ #+-------------------+---------------------------+
register "tcc_offset" = "5" register "tcc_offset" = "10"
register "common_soc_config" = "{ register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,