ipq8064: Make clock code build in coreboot
Include clock.c in the appropriate coreboot stages, modify the code to build cleanly. Use proper pointer cast in .h files. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: I227c871b17e571f6a1db3ada3821dbb1ee884e59 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196407 (cherry picked from commit 75decceccd97298974891bb98b796eccfe11f46c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7d44464d4ca8153e84407fc05a25e2e79e74901e Reviewed-on: http://review.coreboot.org/7271 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
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@ -1,10 +1,13 @@
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bootblock-y += cbfs.c
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bootblock-y += clock.c
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bootblock-y += gpio.c
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romstage-y += cbfs.c
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romstage-y += clock.c
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romstage-y += gpio.c
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ramstage-y += cbfs.c
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ramstage-y += clock.c
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ramstage-y += gpio.c
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ramstage-y += timer.c
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@ -2,11 +2,8 @@
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* Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.
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*/
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#include <common.h>
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#include <asm/arch-ipq806x/clock.h>
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#include <asm/arch-ipq806x/nss/clock.h>
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#include <asm/arch-ipq806x/iomap.h>
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#include <asm/io.h>
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#include <delay.h>
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#include <clock.h>
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/**
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* uart_pll_vote_clk_enable - enables PLL8
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@ -30,10 +30,11 @@
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_IPQ860X_CLOCK_H_
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#define __PLATFORM_IPQ860X_CLOCK_H_
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#ifndef __IPQ860X_CLOCK_H_
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#define __IPQ860X_CLOCK_H_
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#include <iomap.h>
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#include <asm/io.h>
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/* UART clock @ 7.3728 MHz */
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#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
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@ -51,7 +52,7 @@
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#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
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#define BB_PLL_ENA_SC0_REG REG(0x34C0)
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#define BB_PLL8_STATUS_REG REG(0x3158)
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#define REG(off) (MSM_CLK_CTL_BASE + (off))
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#define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off)))
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#define PLL8_STATUS_BIT 16
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#define PLL_LOCK_DET_STATUS_REG REG(0x03420)
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@ -52,7 +52,7 @@
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#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
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#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
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#define GPT_REG(off) (((uint8_t *)(MSM_GPT_BASE)) + (off))
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#define GPT_REG(off) ((void *)(MSM_GPT_BASE + (off)))
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#define DGT_REG(off) (MSM_DGT_BASE + (off))
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#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)
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