soc/intel/cnl: Generate DMAR ACPI table
The platform supports Virtualization Technology for Directed I/O. Generate DMAR acpi table if VT-d feature is enabled. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I4e1ee5244c67affb13947436d81628c5dc665c9e Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
John Zhao
Nico Huber
parent
45d4b17f5e
commit
db3f0e3ebd
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@ -17,19 +17,22 @@
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <device/mmio.h>
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#include <arch/smp/mpspec.h>
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#include <cbmem.h>
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#include <chip.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <ec/google/chromeec/ec.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/acpi.h>
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#include <intelblocks/p2sb.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/systemagent.h>
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#include <string.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <wrdd.h>
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@ -285,3 +288,80 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
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{
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return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
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}
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static unsigned long soc_fill_dmar(unsigned long current)
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{
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struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
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uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
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bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
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if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) {
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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/* Add RMRR entry */
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tmp = current;
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current += acpi_create_dmar_rmrr(current, 0,
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sa_get_gsm_base(), sa_get_tolud_base() - 1);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_rmrr_fixup(tmp, current);
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}
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struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU);
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uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
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bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
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if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
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current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
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bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
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if (vtvc0bar && vtvc0en) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current,
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DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
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current += acpi_create_dmar_ds_ioapic(current,
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2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
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V_P2SB_CFG_IBDF_FUNC);
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current += acpi_create_dmar_ds_msi_hpet(current,
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0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
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V_P2SB_CFG_HBDF_FUNC);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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return current;
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}
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unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current,
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struct acpi_rsdp *rsdp)
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{
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acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
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/* Create DMAR table only if we have VT-d capability
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* and FSP does not override its feature.
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*/
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
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!(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
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return current;
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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return current;
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}
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@ -52,6 +52,15 @@
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#define EDRAM_BASE_ADDRESS 0xfed80000
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#define EDRAM_BASE_SIZE 0x4000
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#define GFXVT_BASE_ADDRESS 0xfed90000
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#define GFXVT_BASE_SIZE 0x1000
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#define IPUVT_BASE_ADDRESS 0xfed92000
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#define IPUVT_BASE_SIZE 0x1000
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#define VTVC0_BASE_ADDRESS 0xfed91000
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#define VTVC0_BASE_SIZE 0x1000
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#define REG_BASE_ADDRESS 0xfc000000
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#define REG_BASE_SIZE 0x1000
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@ -30,10 +30,17 @@
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define CAPID0_A 0xe4
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#define VTD_DISABLE (1 << 23)
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#define BIOS_RESET_CPL 0x5da8
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#define GFXVTBAR 0x5400
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#define EDRAMBAR 0x5408
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#define IPUVTBAR 0x7880
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#define VTVC0BAR 0x5410
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#define REGBAR 0x5420
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#define VTBAR_ENABLED 0x01
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#define VTBAR_MASK 0x7ffffff000ull
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#define MCH_PKG_POWER_LIMIT_LO 0x59a0
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#define MCH_PKG_POWER_LIMIT_HI 0x59a4
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@ -43,4 +50,24 @@
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#define IMRBASE 0x6A40
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#define IMRLIMIT 0x6A48
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#if CONFIG(SOC_INTEL_COFFEELAKE) || CONFIG(SOC_INTEL_WHISKEYLAKE) \
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|| CONFIG(SOC_INTEL_COMETLAKE)
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static const struct sa_mmio_descriptor soc_vtd_resources[] = {
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{ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
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{ VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
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};
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#else
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static const struct sa_mmio_descriptor soc_vtd_resources[] = {
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{ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
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{ IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" },
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{ VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
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};
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#endif
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#define V_P2SB_CFG_IBDF_BUS 0
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#define V_P2SB_CFG_IBDF_DEV 30
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#define V_P2SB_CFG_IBDF_FUNC 7
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#define V_P2SB_CFG_HBDF_BUS 0
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#define V_P2SB_CFG_HBDF_DEV 30
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#define V_P2SB_CFG_HBDF_FUNC 6
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#endif
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@ -18,10 +18,12 @@
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#include <device/device.h>
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#include <delay.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <intelblocks/systemagent.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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/*
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* SoC implementation
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@ -31,6 +33,8 @@
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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const struct soc_intel_cannonlake_config *const config = dev->chip_info;
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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@ -54,6 +58,15 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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/* Add Vt-d resources if VT-d is enabled. */
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
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return;
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if (!(config && config->VtdDisable)) {
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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ARRAY_SIZE(soc_vtd_resources));
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}
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}
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/*
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