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sb/amd/cimx/sb800: Const'ify pci_devfn_t devices 

Change-Id: I25a6c3ac2426881c6b3f6390ffdc76f08944b7fa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Elyes HAOUAS 2020-04-22 16:10:14 +02:00 committed by Michał Żygowski
parent 49f63e0aa1
commit db4f3bacce
1 changed files with 3 additions and 5 deletions
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8
src/southbridge/amd/cimx/sb800/bootblock.c
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@ -9,9 +9,7 @@ static void enable_rom(void)
{ {
u16 word; u16 word;
u32 dword; u32 dword;
pci_devfn_t dev; const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
dev = PCI_DEV(0, 0x14, 0x03);
/* SB800 LPC Bridge 0:20:3:44h. /* SB800 LPC Bridge 0:20:3:44h.
* BIT6: Port Enable for serial port 0x3f8-0x3ff * BIT6: Port Enable for serial port 0x3f8-0x3ff
* BIT29: Port Enable for KBC port 0x60 and 0x64 * BIT29: Port Enable for KBC port 0x60 and 0x64
@ -43,7 +41,7 @@ static void enable_rom(void)
static void enable_prefetch(void) static void enable_prefetch(void)
{ {
u32 dword; u32 dword;
pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
/* Enable PrefetchEnSPIFromHost */ /* Enable PrefetchEnSPIFromHost */
dword = pci_s_read_config32(dev, 0xb8); dword = pci_s_read_config32(dev, 0xb8);
@ -53,7 +51,7 @@ static void enable_prefetch(void)
static void enable_spi_fast_mode(void) static void enable_spi_fast_mode(void)
{ {
u32 dword; u32 dword;
pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
// set temp MMIO base // set temp MMIO base
volatile u32 *spi_base = (void *)0xa0000000; volatile u32 *spi_base = (void *)0xa0000000;