GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard: add support for lenovo x1 carbon gen 1 

Based on Thinkpad x230 and schematics.
Verified by autoport.

USB debug port is the left front usb port

Thanks to Holger Levsen for the device.

Change-Id: I97c8e01a3ce0577d7dc9e8df7d33db3b155fe3d6
Tested-on: lenovo x1 carbon gen 1
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16994
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Alexander Couzens 2016-10-12 04:44:19 +02:00 committed by Martin Roth
parent 7ee81a4a01
commit db508565d2
21 changed files with 1518 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

76
src/mainboard/lenovo/x1_carbon_gen1/Kconfig Normal file
View File

@ -0,0 +1,76 @@
if BOARD_LENOVO_X1_CARBON_GEN1
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select USE_NATIVE_RAMINIT
select SOUTHBRIDGE_INTEL_C216
select EC_LENOVO_PMH7
select EC_LENOVO_H8
select NO_UART_ON_SUPERIO
select BOARD_ROMSIZE_KB_12288
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select INTEL_INT15
select SANDYBRIDGE_IVYBRIDGE_LVDS
select DRIVERS_RICOH_RCE822
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_LIBGFXINIT
select GFX_GMA_INTERNAL_IS_LVDS
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE
config HAVE_IFD_BIN
bool
default n
config HAVE_ME_BIN
bool
default n
config MAINBOARD_DIR
string
default lenovo/x1_carbon_gen1
config MAINBOARD_PART_NUMBER
string
default "ThinkPad X1 carbon gen 1"
config MMCONF_BASE_ADDRESS
hex
default 0xf8000000
config MAX_CPUS
int
default 8
config USBDEBUG_HCD_INDEX
int
default 2
config DRAM_RESET_GATE_GPIO
int
default 10
config VGA_BIOS_FILE
string
default "pci8086,0166.rom"
config VGA_BIOS_ID
string
default "8086,0166"
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x17aa
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x21fa
endif # BOARD_LENOVO_X1_CARBON_GEN1

2
src/mainboard/lenovo/x1_carbon_gen1/Kconfig.name Normal file
View File

@ -0,0 +1,2 @@
config BOARD_LENOVO_X1_CARBON_GEN1
bool "ThinkPad X1 carbon gen 1"

21
src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc Normal file
View File

@ -0,0 +1,21 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
subdirs-y += spd
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

21
src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl Normal file
View File

@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <ec/lenovo/h8/acpi/ec.asl>
Scope(\_SB.PCI0.LPCB.EC)
{
}

35
src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl Normal file
View File

@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method(_PTS,1)
{
\_SB.PCI0.LPCB.EC.RADI(0)
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
/* ME may not be up yet. */
Store (0, \_TZ.MEB1)
Store (0, \_TZ.MEB2)
/* Not implemented. */
Return(Package(){0,0})
}

1
src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl Normal file
View File

@ -0,0 +1 @@
#include <drivers/pc80/pc/ps2_controller.asl>

56
src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c Normal file
View File

@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
}
void acpi_create_gnvs(global_nvs_t *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
gnvs->s3u1 = 0;
/* Disable USB ports in S5 by default */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* IGD Displays */
// the lid is open by default.
gnvs->lids = 1;
acpi_update_thermal_table(gnvs);
}

6
src/mainboard/lenovo/x1_carbon_gen1/board_info.txt Normal file
View File

@ -0,0 +1,6 @@
Category: laptop
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: n
Release year: 2012

17
src/mainboard/lenovo/x1_carbon_gen1/cmos.default Normal file
View File

@ -0,0 +1,17 @@
boot_option=Fallback
baud_rate=115200
debug_level=Spew
power_on_after_fail=Disable
nmi=Enable
volume=0x3
first_battery=Primary
bluetooth=Enable
wwan=Enable
wlan=Enable
touchpad=Enable
sata_mode=AHCI
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
hyper_threading=Enable
backlight=Both

142
src/mainboard/lenovo/x1_carbon_gen1/cmos.layout Normal file
View File

@ -0,0 +1,142 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
## Copyright (C) 2014 Vladimir Serbinenko
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
392 3 e 5 baud_rate
395 4 e 6 debug_level
#399 1 r 0 unused
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: EC
411 1 e 8 first_battery
412 1 e 1 bluetooth
413 1 e 1 wwan
414 1 e 1 touchpad
415 1 e 1 wlan
416 1 e 1 trackpoint
417 1 e 1 fn_ctrl_swap
418 1 e 1 sticky_fn
#419 2 r 0 unused
421 1 e 9 sata_mode
422 2 e 10 backlight
# coreboot config options: cpu
424 1 e 2 hyper_threading
#425 7 r 0 unused
# coreboot config options: northbridge
432 3 e 11 gfx_uma_size
#435 5 r 0 unused
440 8 h 0 volume
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 Secondary
8 1 Primary
9 0 AHCI
9 1 Compatible
10 0 Both
10 1 Keyboard only
10 2 Thinklight only
10 3 None
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
# -----------------------------------------------------------------
checksums
checksum 392 415 984

183
src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb Normal file
View File

@ -0,0 +1,183 @@
chip northbridge/intel/sandybridge
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.ndid" = "3"
register "gfx.use_spread_spectrum_clock" = "1"
register "gpu_cpu_backlight" = "0x00001155"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4"
register "gpu_panel_port_select" = "0"
register "gpu_panel_power_backlight_off_delay" = "2000"
register "gpu_panel_power_backlight_on_delay" = "3000"
register "gpu_panel_power_cycle_delay" = "6"
register "gpu_panel_power_down_delay" = "300"
register "gpu_panel_power_up_delay" = "300"
register "gpu_pch_backlight" = "0x11551155"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
end
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
end
end
register "pci_mmio_size" = "1024"
device domain 0 on
device pci 00.0 on
subsystemid 0x17aa 0x21fa
end # host bridge
device pci 01.0 off end # PCIe Bridge for discrete graphics
device pci 02.0 on
subsystemid 0x17aa 0x21fa
end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) 2 (msata)
register "sata_port_map" = "0x5"
# Set max SATA speed to 6.0 Gb/s
register "sata_interface_speed_support" = "0x3"
register "gen1_dec" = "0x7c1601"
register "gen2_dec" = "0x0c15e1"
register "gen3_dec" = "0x000000"
register "gen4_dec" = "0x0c06a1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf"
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
device pci 14.0 on
subsystemid 0x17aa 0x21f9
end # USB 3.0 Controller
device pci 16.0 on
subsystemid 0x17aa 0x21f9
end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on
subsystemid 0x17aa 0x21f9
end # USB2 EHCI #2
device pci 1b.0 on
subsystemid 0x17aa 0x21f9
end # High Definition Audio
device pci 1c.0 on
subsystemid 0x17aa 0x21f9
chip drivers/ricoh/rce822
register "sdwppol" = "0"
register "disable_mask" = "0x87"
device pci 00.0 on
subsystemid 0x17aa 0x21f3
end
end
end # PCIe Port #1
device pci 1c.1 on
subsystemid 0x17aa 0x21f9
end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on
subsystemid 0x17aa 0x21f9
end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on #LPC bridge
subsystemid 0x17aa 0x21f9
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
end
register "backlight_enable" = "0x01"
register "dock_event_enable" = "0x01"
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62
io 0x62 = 0x66
io 0x64 = 0x1600
io 0x66 = 0x1604
end
register "has_keyboard_backlight" = "1"
register "beepmask0" = "0x00"
register "beepmask1" = "0x86"
register "config0" = "0xa6"
register "config1" = "0x05"
register "config2" = "0xa0"
register "config3" = "0xc0"
register "event2_enable" = "0xff"
register "event3_enable" = "0xff"
register "event4_enable" = "0xc0"
register "event5_enable" = "0x3c"
register "event7_enable" = "0x01"
register "event8_enable" = "0x7b"
register "event9_enable" = "0xff"
register "eventc_enable" = "0xff"
register "eventd_enable" = "0xff"
register "evente_enable" = "0x0d"
end
end # LPC bridge
device pci 1f.2 on
subsystemid 0x17aa 0x21f9
end # SATA Controller 1
device pci 1f.3 on
subsystemid 0x17aa 0x21f9
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
device i2c 55 on end
device i2c 56 on end
device i2c 57 on end
device i2c 5c on end
device i2c 5d on end
device i2c 5e on end
device i2c 5f on end
end
end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on
subsystemid 0x17aa 0x21f9
end # Thermal
end
end
end

56
src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl Normal file
View File

@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define THINKPAD_EC_GPE 17
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, // DSDT revision: ACPI v3.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20141018 // OEM revision
)
{
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
// Some generic macros
#include "acpi/platform.asl"
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}

19
src/mainboard/lenovo/x1_carbon_gen1/gma-mainboard.ads Normal file
View File

@ -0,0 +1,19 @@
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(DP1,
DP2,
DP3,
HDMI1,
HDMI2,
HDMI3,
Internal,
others => Disabled);
end GMA.Mainboard;

449
src/mainboard/lenovo/x1_carbon_gen1/gpio.c Normal file
View File

@ -0,0 +1,449 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_GPIO,
.gpio11 = GPIO_MODE_NATIVE,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_NATIVE,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_NATIVE,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_NATIVE,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_GPIO,
.gpio26 = GPIO_MODE_GPIO,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_OUTPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_OUTPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio18 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio20 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio22 = GPIO_DIR_OUTPUT,
.gpio23 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_INPUT,
.gpio26 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio29 = GPIO_DIR_OUTPUT,
.gpio30 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio0 = GPIO_LEVEL_HIGH,
.gpio1 = GPIO_LEVEL_HIGH,
.gpio2 = GPIO_LEVEL_LOW,
.gpio3 = GPIO_LEVEL_HIGH,
.gpio4 = GPIO_LEVEL_HIGH,
.gpio5 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_HIGH,
.gpio7 = GPIO_LEVEL_HIGH,
.gpio8 = GPIO_LEVEL_LOW,
.gpio9 = GPIO_LEVEL_HIGH,
.gpio10 = GPIO_LEVEL_HIGH,
.gpio11 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_LOW,
.gpio13 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio16 = GPIO_LEVEL_HIGH,
.gpio17 = GPIO_LEVEL_HIGH,
.gpio18 = GPIO_LEVEL_HIGH,
.gpio19 = GPIO_LEVEL_HIGH,
.gpio20 = GPIO_LEVEL_HIGH,
.gpio21 = GPIO_LEVEL_HIGH,
.gpio22 = GPIO_LEVEL_HIGH,
.gpio23 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_LOW,
.gpio25 = GPIO_LEVEL_LOW,
.gpio26 = GPIO_LEVEL_LOW,
.gpio27 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
.gpio29 = GPIO_LEVEL_HIGH,
.gpio30 = GPIO_LEVEL_HIGH,
.gpio31 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set1 pch_gpio_set1_reset = {
.gpio0 = GPIO_RESET_PWROK,
.gpio1 = GPIO_RESET_PWROK,
.gpio2 = GPIO_RESET_PWROK,
.gpio3 = GPIO_RESET_PWROK,
.gpio4 = GPIO_RESET_PWROK,
.gpio5 = GPIO_RESET_PWROK,
.gpio6 = GPIO_RESET_PWROK,
.gpio7 = GPIO_RESET_PWROK,
.gpio8 = GPIO_RESET_PWROK,
.gpio9 = GPIO_RESET_PWROK,
.gpio10 = GPIO_RESET_PWROK,
.gpio11 = GPIO_RESET_PWROK,
.gpio12 = GPIO_RESET_PWROK,
.gpio13 = GPIO_RESET_PWROK,
.gpio14 = GPIO_RESET_PWROK,
.gpio15 = GPIO_RESET_PWROK,
.gpio16 = GPIO_RESET_PWROK,
.gpio17 = GPIO_RESET_PWROK,
.gpio18 = GPIO_RESET_PWROK,
.gpio19 = GPIO_RESET_PWROK,
.gpio20 = GPIO_RESET_PWROK,
.gpio21 = GPIO_RESET_PWROK,
.gpio22 = GPIO_RESET_PWROK,
.gpio23 = GPIO_RESET_PWROK,
.gpio24 = GPIO_RESET_PWROK,
.gpio25 = GPIO_RESET_PWROK,
.gpio26 = GPIO_RESET_PWROK,
.gpio27 = GPIO_RESET_PWROK,
.gpio28 = GPIO_RESET_PWROK,
.gpio29 = GPIO_RESET_PWROK,
.gpio30 = GPIO_RESET_PWROK,
.gpio31 = GPIO_RESET_PWROK,
};
const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_NO_INVERT,
.gpio1 = GPIO_INVERT,
.gpio2 = GPIO_NO_INVERT,
.gpio3 = GPIO_NO_INVERT,
.gpio4 = GPIO_NO_INVERT,
.gpio5 = GPIO_NO_INVERT,
.gpio6 = GPIO_INVERT,
.gpio7 = GPIO_NO_INVERT,
.gpio8 = GPIO_NO_INVERT,
.gpio9 = GPIO_NO_INVERT,
.gpio10 = GPIO_NO_INVERT,
.gpio11 = GPIO_NO_INVERT,
.gpio12 = GPIO_NO_INVERT,
.gpio13 = GPIO_INVERT,
.gpio14 = GPIO_NO_INVERT,
.gpio15 = GPIO_NO_INVERT,
.gpio16 = GPIO_NO_INVERT,
.gpio17 = GPIO_NO_INVERT,
.gpio18 = GPIO_NO_INVERT,
.gpio19 = GPIO_NO_INVERT,
.gpio20 = GPIO_NO_INVERT,
.gpio21 = GPIO_NO_INVERT,
.gpio22 = GPIO_NO_INVERT,
.gpio23 = GPIO_NO_INVERT,
.gpio24 = GPIO_NO_INVERT,
.gpio25 = GPIO_NO_INVERT,
.gpio26 = GPIO_NO_INVERT,
.gpio27 = GPIO_NO_INVERT,
.gpio28 = GPIO_NO_INVERT,
.gpio29 = GPIO_NO_INVERT,
.gpio30 = GPIO_NO_INVERT,
.gpio31 = GPIO_NO_INVERT,
};
const struct pch_gpio_set1 pch_gpio_set1_blink = {
.gpio0 = GPIO_NO_BLINK,
.gpio1 = GPIO_NO_BLINK,
.gpio2 = GPIO_NO_BLINK,
.gpio3 = GPIO_NO_BLINK,
.gpio4 = GPIO_NO_BLINK,
.gpio5 = GPIO_NO_BLINK,
.gpio6 = GPIO_NO_BLINK,
.gpio7 = GPIO_NO_BLINK,
.gpio8 = GPIO_NO_BLINK,
.gpio9 = GPIO_NO_BLINK,
.gpio10 = GPIO_NO_BLINK,
.gpio11 = GPIO_NO_BLINK,
.gpio12 = GPIO_NO_BLINK,
.gpio13 = GPIO_NO_BLINK,
.gpio14 = GPIO_NO_BLINK,
.gpio15 = GPIO_NO_BLINK,
.gpio16 = GPIO_NO_BLINK,
.gpio17 = GPIO_NO_BLINK,
.gpio18 = GPIO_NO_BLINK,
.gpio19 = GPIO_NO_BLINK,
.gpio20 = GPIO_NO_BLINK,
.gpio21 = GPIO_NO_BLINK,
.gpio22 = GPIO_NO_BLINK,
.gpio23 = GPIO_NO_BLINK,
.gpio24 = GPIO_NO_BLINK,
.gpio25 = GPIO_NO_BLINK,
.gpio26 = GPIO_NO_BLINK,
.gpio27 = GPIO_NO_BLINK,
.gpio28 = GPIO_NO_BLINK,
.gpio29 = GPIO_NO_BLINK,
.gpio30 = GPIO_NO_BLINK,
.gpio31 = GPIO_NO_BLINK,
};
const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_NATIVE,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_GPIO,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_GPIO,
.gpio44 = GPIO_MODE_GPIO,
.gpio45 = GPIO_MODE_GPIO,
.gpio46 = GPIO_MODE_NATIVE,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_GPIO,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_GPIO,
.gpio60 = GPIO_MODE_NATIVE,
.gpio61 = GPIO_MODE_NATIVE,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_INPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio40 = GPIO_DIR_INPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_OUTPUT,
.gpio44 = GPIO_DIR_INPUT,
.gpio45 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio47 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_OUTPUT,
.gpio52 = GPIO_DIR_OUTPUT,
.gpio53 = GPIO_DIR_OUTPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_OUTPUT,
.gpio56 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio58 = GPIO_DIR_INPUT,
.gpio59 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_INPUT,
.gpio61 = GPIO_DIR_OUTPUT,
.gpio62 = GPIO_DIR_OUTPUT,
.gpio63 = GPIO_DIR_OUTPUT,
};
const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio34 = GPIO_LEVEL_LOW,
.gpio35 = GPIO_LEVEL_LOW,
.gpio36 = GPIO_LEVEL_LOW,
.gpio37 = GPIO_LEVEL_LOW,
.gpio38 = GPIO_LEVEL_LOW,
.gpio39 = GPIO_LEVEL_LOW,
.gpio40 = GPIO_LEVEL_HIGH,
.gpio41 = GPIO_LEVEL_HIGH,
.gpio42 = GPIO_LEVEL_HIGH,
.gpio43 = GPIO_LEVEL_HIGH,
.gpio44 = GPIO_LEVEL_HIGH,
.gpio45 = GPIO_LEVEL_LOW,
.gpio46 = GPIO_LEVEL_HIGH,
.gpio47 = GPIO_LEVEL_HIGH,
.gpio48 = GPIO_LEVEL_HIGH,
.gpio49 = GPIO_LEVEL_HIGH,
.gpio50 = GPIO_LEVEL_HIGH,
.gpio51 = GPIO_LEVEL_HIGH,
.gpio52 = GPIO_LEVEL_HIGH,
.gpio53 = GPIO_LEVEL_HIGH,
.gpio54 = GPIO_LEVEL_HIGH,
.gpio55 = GPIO_LEVEL_HIGH,
.gpio56 = GPIO_LEVEL_LOW,
.gpio57 = GPIO_LEVEL_HIGH,
.gpio58 = GPIO_LEVEL_HIGH,
.gpio59 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
.gpio61 = GPIO_LEVEL_HIGH,
.gpio62 = GPIO_LEVEL_HIGH,
.gpio63 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set2 pch_gpio_set2_reset = {
.gpio32 = GPIO_RESET_PWROK,
.gpio33 = GPIO_RESET_PWROK,
.gpio34 = GPIO_RESET_PWROK,
.gpio35 = GPIO_RESET_PWROK,
.gpio36 = GPIO_RESET_PWROK,
.gpio37 = GPIO_RESET_PWROK,
.gpio38 = GPIO_RESET_PWROK,
.gpio39 = GPIO_RESET_PWROK,
.gpio40 = GPIO_RESET_PWROK,
.gpio41 = GPIO_RESET_PWROK,
.gpio42 = GPIO_RESET_PWROK,
.gpio43 = GPIO_RESET_PWROK,
.gpio44 = GPIO_RESET_PWROK,
.gpio45 = GPIO_RESET_PWROK,
.gpio46 = GPIO_RESET_PWROK,
.gpio47 = GPIO_RESET_PWROK,
.gpio48 = GPIO_RESET_PWROK,
.gpio49 = GPIO_RESET_PWROK,
.gpio50 = GPIO_RESET_PWROK,
.gpio51 = GPIO_RESET_PWROK,
.gpio52 = GPIO_RESET_PWROK,
.gpio53 = GPIO_RESET_PWROK,
.gpio54 = GPIO_RESET_PWROK,
.gpio55 = GPIO_RESET_PWROK,
.gpio56 = GPIO_RESET_PWROK,
.gpio57 = GPIO_RESET_PWROK,
.gpio58 = GPIO_RESET_PWROK,
.gpio59 = GPIO_RESET_PWROK,
.gpio60 = GPIO_RESET_PWROK,
.gpio61 = GPIO_RESET_PWROK,
.gpio62 = GPIO_RESET_PWROK,
.gpio63 = GPIO_RESET_PWROK,
};
const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_GPIO,
.gpio65 = GPIO_MODE_GPIO,
.gpio66 = GPIO_MODE_GPIO,
.gpio67 = GPIO_MODE_GPIO,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_GPIO,
.gpio71 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_NATIVE,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_NATIVE,
.gpio75 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio64 = GPIO_DIR_INPUT,
.gpio65 = GPIO_DIR_INPUT,
.gpio66 = GPIO_DIR_INPUT,
.gpio67 = GPIO_DIR_INPUT,
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio71 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_INPUT,
.gpio73 = GPIO_DIR_INPUT,
.gpio74 = GPIO_DIR_INPUT,
.gpio75 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio64 = GPIO_LEVEL_LOW,
.gpio65 = GPIO_LEVEL_LOW,
.gpio66 = GPIO_LEVEL_LOW,
.gpio67 = GPIO_LEVEL_LOW,
.gpio68 = GPIO_LEVEL_LOW,
.gpio69 = GPIO_LEVEL_LOW,
.gpio70 = GPIO_LEVEL_HIGH,
.gpio71 = GPIO_LEVEL_HIGH,
.gpio72 = GPIO_LEVEL_HIGH,
.gpio73 = GPIO_LEVEL_HIGH,
.gpio74 = GPIO_LEVEL_HIGH,
.gpio75 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set3 pch_gpio_set3_reset = {
.gpio64 = GPIO_RESET_PWROK,
.gpio65 = GPIO_RESET_PWROK,
.gpio66 = GPIO_RESET_PWROK,
.gpio67 = GPIO_RESET_PWROK,
.gpio68 = GPIO_RESET_PWROK,
.gpio69 = GPIO_RESET_PWROK,
.gpio70 = GPIO_RESET_PWROK,
.gpio71 = GPIO_RESET_PWROK,
.gpio72 = GPIO_RESET_PWROK,
.gpio73 = GPIO_RESET_PWROK,
.gpio74 = GPIO_RESET_PWROK,
.gpio75 = GPIO_RESET_PWROK,
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

75
src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c Normal file
View File

@ -0,0 +1,75 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0269, /* Codec Vendor / Device ID: Realtek */
0x17aa21f9, /* Subsystem ID */
0x0000000b, /* Number of 4 dword sets */
/* NID 0x01: Subsystem ID. */
AZALIA_SUBVENDOR(0x0, 0x17aa21f9),
/* NID 0x12. */
AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140),
/* NID 0x14. */
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
/* NID 0x15. */
AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
/* NID 0x17. */
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
/* NID 0x18. */
AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830),
/* NID 0x19. */
AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
/* NID 0x1a. */
AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
/* NID 0x1b. */
AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
/* NID 0x1d. */
AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205),
/* NID 0x1e. */
AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
0x80862806, /* Codec Vendor / Device ID: Intel */
0x80860101, /* Subsystem ID */
0x00000004, /* Number of 4 dword sets */
/* NID 0x01: Subsystem ID. */
AZALIA_SUBVENDOR(0x3, 0x80860101),
/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

55
src/mainboard/lenovo/x1_carbon_gen1/mainboard.c Normal file
View File

@ -0,0 +1,55 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011-2012 Google Inc.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h>
#include <arch/acpi.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <device/pci.h>
#include <pc80/keyboard.h>
#include <ec/lenovo/h8/h8.h>
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
RCBA32(0x38c0) = 0x00000007;
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
/* TODO: this device doesnt have a dock */
void h8_mainboard_init_dock (void)
{
}

130
src/mainboard/lenovo/x1_carbon_gen1/romstage.c Normal file
View File

@ -0,0 +1,130 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
* Copyright (C) 2017 Alexander Couzens <lynxis@fe80.eu>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <string.h>
#include <lib.h>
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cbfs.h>
void pch_enable_lpc(void)
{
/* X230 EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, 0xac,
0x80010000);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled, current, OC pin */
{ 0, 3, 0 }, /* P00 disconnected */
{ 1, 1, 1 }, /* P01 left or right */
{ 0, 1, 3 }, /* P02 disconnected */
{ 1, 3, -1 },/* P03 WWAN */
{ 0, 1, 2 }, /* P04 disconnected */
{ 0, 1, -1 },/* P05 disconnected */
{ 0, 1, -1 },/* P06 disconnected */
{ 0, 2, -1 },/* P07 disconnected */
{ 0, 1, -1 },/* P08 disconnected */
{ 1, 2, 5 }, /* P09 left or right */
{ 1, 3, -1 },/* P10 FPR */
{ 1, 3, -1 },/* P11 Bluetooth */
{ 1, 1, -1 },/* P12 WLAN */
{ 1, 1, -1 },/* P13 Camera */
};
static uint8_t *get_spd_data(int spd_index)
{
uint8_t *spd_file;
size_t spd_file_len;
printk(BIOS_DEBUG, "spd index %d\n", spd_index);
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
&spd_file_len);
if (!spd_file)
die("SPD data not found.");
if (spd_file_len < spd_index * 256)
die("Missing SPD data.");
return spd_file + spd_index * 256;
}
void rcba_config(void)
{
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
uint8_t *memory;
const int spd_gpio_vector[] = {25, 45, -1};
int spd_index = get_gpios(spd_gpio_vector);
/* 4gb model = 0, 8gb model = 1 */
/* int extended_memory_version = get_gpio(44); */
/* TODO: how do they differ? Guess only one slot is connected */
/*
* GPIO45 GPIO25
* 0 0 elpida
* 0 1 hynix
* 1 0 samsung
* 1 1 reserved
*/
/* we only support elpida. Because the spd data is missing */
if (spd_index != 0)
die("Unsupported Memory. Please add your SPD dump to coreboot.");
memory = get_spd_data(spd_index);
memcpy(&spd[0], memory, 256);
memcpy(&spd[2], memory, 256);
}
void mainboard_early_init(int s3resume)
{
}
void mainboard_config_superio(void)
{
}

101
src/mainboard/lenovo/x1_carbon_gen1/smihandler.c Normal file
View File

@ -0,0 +1,101 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
#include <southbridge/intel/bd82x6x/pch.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
static void mainboard_smm_init(void)
{
printk(BIOS_DEBUG, "initializing SMI\n");
/* Enable 0x1600/0x1600 register pair */
ec_set_bit(0x00, 0x05);
}
int mainboard_io_trap_handler(int smif)
{
static int smm_initialized;
if (!smm_initialized) {
mainboard_smm_init();
smm_initialized = 1;
}
return 0;
}
static void mainboard_smi_handle_ec_sci(void)
{
u8 status = inb(EC_SC);
u8 event;
if (!(status & EC_SCI_EVT))
return;
event = ec_query();
printk(BIOS_DEBUG, "EC event %02x\n", event);
}
void mainboard_smi_gpi(u32 gpi_sts)
{
if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci();
}
int mainboard_smi_apmc(u8 data)
{
switch (data) {
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
/* route EC_SCI to SCI */
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
/* discard all events, and enable attention */
ec_write(0x80, 0x01);
break;
case APM_CNT_ACPI_DISABLE:
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
/* route EC_SCI to SMI */
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
/* discard all events, and enable attention */
ec_write(0x80, 0x01);
break;
default:
break;
}
return 0;
}
void mainboard_smi_sleep(u8 slp_typ)
{
if (slp_typ == 3) {
u8 ec_wake = ec_read(0x32);
/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
if (ec_wake & 0x14) {
/* Redirect EC WAKE GPE to SCI. */
gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
}
}
}

31
src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc Normal file
View File

@ -0,0 +1,31 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 Alexander Couzens <lynxis@fe80.eu>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
SPD_BIN = $(obj)/spd.bin
SPD_SOURCES = elpida.hex # 0b0000 Single Channel 2GB
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f))
# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
do printf $$(printf '\%o' 0x$$c); \
done; \
done > $@
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := spd

16
src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.hex Normal file
View File

@ -0,0 +1,16 @@
92 11 0b 03 04 00 00 01 03 52 01 08 0c 00 20 00
6c 78 6c 30 6c 11 20 81 f8 0a 3c 3c 01 68 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 63 35
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

26
src/mainboard/lenovo/x1_carbon_gen1/thermal.h Normal file
View File

@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef X230_THERMAL_H
#define X230_THERMAL_H
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 100
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
#endif