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mainboard/intel/amenia: Configure PERST_0 pin 

Configure PERST_0 and assign the pin in devicetree.

BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.

Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16350
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vaibhav Shankar 2016-08-26 19:10:21 -07:00 committed by Aaron Durbin
parent 7e10c8209b
commit db54bb5e3a
2 changed files with 6 additions and 1 deletions
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5
src/mainboard/intel/amenia/devicetree.cb
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@ -7,6 +7,11 @@ chip soc/intel/apollolake
register "pcie_rp0_clkreq_pin" = "3" # wifi/bt
register "pcie_rp2_clkreq_pin" = "0" # SSD
# GPIO for PERST_0
# If PERST_0 is defined assign the GPIO
# If PERST_0 is not defined assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_122"
# eMMC TX DATA Delay 1#
# 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200

2
src/mainboard/intel/amenia/gpio.h
View File

@ -223,7 +223,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPIO_119, DN_20K), /* GP_SSP_2_FS0 */
PAD_NC(GPIO_120, DN_20K), /* GP_SSP_2_FS1 */
PAD_NC(GPIO_121, DN_20K), /* GP_SSP_2_FS2 */
PAD_NC(GPIO_122, DN_20K), /* GP_SSP_2_RXD */
PAD_CFG_GPO(GPIO_122, 0, DEEP), /* WIFI PERST_0 */
PAD_NC(GPIO_123, DN_20K), /* GP_SSP_2_TXD */
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