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Asrock E350M1: Use SPD read code from F14 wrapper 

Changes:
 - Get rid of the E350M1 mainboard specific code and use the
   platform generic function wrapper that was added in change
   http://review.coreboot.org/#/c/2497/
   AMD f14: Add SPD read functions to wrapper code

 - Move DIMM addresses into devicetree.cb

 - Add the ASF init that used to be in the SPD read code into
   mainboard_enable()

Notes:
 - The DIMM reads only happen in romstage, so the function is not
   available in ramstage.  Point the read-SPD callback to a generic
   function in ramstage.

Change-Id: I08c2aebc62facc14f94400ee1ad188901ba73f19
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2875
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
This commit is contained in:
Jens Rottmann 2013-03-21 22:21:28 +01:00 committed by Stefan Reinauer
parent 3db86ccfd7
commit db6c5bfd8b
5 changed files with 22 additions and 170 deletions
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7
src/mainboard/asrock/e350m1/BiosCallOuts.c
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@ -22,6 +22,7 @@
#include "BiosCallOuts.h" #include "BiosCallOuts.h"
#include "heapManager.h" #include "heapManager.h"
#include "SB800.h" #include "SB800.h"
#include <northbridge/amd/agesa/family14/dimmSpd.h>
CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = CONST BIOS_CALLOUT_STRUCT BiosCallouts[] =
{ {
@ -421,7 +422,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); #ifdef __PRE_RAM__
Status = agesa_ReadSPD (Func, Data, ConfigPtr);
#else
Status = AGESA_UNSUPPORTED;
#endif
return Status; return Status;
} }

2
src/mainboard/asrock/e350m1/Makefile.inc
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@ -19,13 +19,11 @@
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c romstage-y += agesawrapper.c
romstage-y += dimmSpd.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c ramstage-y += agesawrapper.c
ramstage-y += dimmSpd.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

7
src/mainboard/asrock/e350m1/devicetree.cb
View File

@ -125,6 +125,13 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.5 on end device pci 18.5 on end
device pci 18.6 on end device pci 18.6 on end
device pci 18.7 on end device pci 18.7 on end
register "spdAddrLookup" = "
{
{ {0xA0, 0xA4}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #domain end #domain
end #northbridge/amd/agesa/family14/root_complex end #northbridge/amd/agesa/family14/root_complex

167
src/mainboard/asrock/e350m1/dimmSpd.c
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@ -1,167 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
/*#pragma optimize ("", off) // for source level debug
*---------------------------------------------------------------------------
*
* SPD address table - porting required
*/
static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm
{
// socket 0
{
{0xA0, 0xA4}, // channel 0 dimms
{0x00, 0x00}, // channel 1 dimms
},
// socket 1
{
{0x00, 0x00}, // channel 0 dimms
{0x00, 0x00}, // channel 1 dimms
},
};
/*-----------------------------------------------------------------------------
*
* readSmbusByteData - read a single SPD byte from any offset
*/
static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
{
unsigned int status;
UINT64 limit;
address |= 1; // set read bit
__outbyte (iobase + 0, 0xFF); // clear error status
__outbyte (iobase + 1, 0x1F); // clear error status
__outbyte (iobase + 3, offset); // offset in eeprom
__outbyte (iobase + 4, address); // slave address and read bit
__outbyte (iobase + 2, 0x48); // read byte command
// time limit to avoid hanging for unexpected error status (should never happen)
limit = __rdtsc () + 2000000000 / 10;
for (;;)
{
status = __inbyte (iobase);
if (__rdtsc () > limit) break;
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
buffer [0] = __inbyte (iobase + 5);
if (status == 2) status = 0; // check for done with no errors
return status;
}
/*-----------------------------------------------------------------------------
*
* readSmbusByte - read a single SPD byte from the default offset
* this function is faster function readSmbusByteData
*/
static int readSmbusByte (int iobase, int address, char *buffer)
{
unsigned int status;
UINT64 limit;
__outbyte (iobase + 0, 0xFF); // clear error status
__outbyte (iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status
limit = __rdtsc () + 2000000000 / 10;
for (;;)
{
status = __inbyte (iobase);
if (__rdtsc () > limit) break;
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
buffer [0] = __inbyte (iobase + 5);
if (status == 2) status = 0; // check for done with no errors
return status;
}
/*---------------------------------------------------------------------------
*
* readspd - Read one or more SPD bytes from a DIMM.
* Start with offset zero and read sequentially.
* Optimization relies on autoincrement to avoid
* sending offset for every byte.
* Reads 128 bytes in 7-8 ms at 400 KHz.
*/
static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
{
int index, error;
/* read the first byte using offset zero */
error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
if (error) return error;
/* read the remaining bytes using auto-increment for speed */
for (index = 1; index < count; index++)
{
error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
if (error) return error;
}
return 0;
}
static void writePmReg (int reg, int data)
{
__outbyte (0xCD6, reg);
__outbyte (0xCD7, data);
}
static void setupFch (int ioBase)
{
writePmReg (0x2D, ioBase >> 8);
writePmReg (0x2C, ioBase | 1);
writePmReg (0x29, 0x80);
writePmReg (0x28, 0x61);
__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
}
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
{
int spdAddress, ioBase;
if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
if (spdAddress == 0) return AGESA_ERROR;
ioBase = SMBUS0_BASE_ADDRESS;
setupFch (ioBase);
return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
}

9
src/mainboard/asrock/e350m1/mainboard.c
View File

@ -53,6 +53,15 @@ void set_pcie_dereset(void)
static void mainboard_enable(device_t dev) static void mainboard_enable(device_t dev)
{ {
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/*
* Initialize ASF registers to an arbitrary address because someone
* long ago set things up this way inside the SPD read code. The
* SPD read code has been made generic and moved out of the board
* directory, so the ASF init is being done here.
*/
pm_iowrite(0x29, 0x80);
pm_iowrite(0x28, 0x61);
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {