drivers/tpm: Add TPM ramstage driver for devices without vboot.

Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.

* Add TPM driver in ramstage chip init which calls the tpm_setup
  function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
  in ramstage.

Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/haswell/romstage.c

@@ -42,7 +42,6 @@
 #include "northbridge/intel/haswell/raminit.h"
 #include "southbridge/intel/lynxpoint/pch.h"
 #include "southbridge/intel/lynxpoint/me.h"
-#include <security/tpm/tspi.h>
 #include <cpu/intel/romstage.h>
 
 static inline void reset_system(void)
@@ -157,6 +156,4 @@ void romstage_common(const struct romstage_params *params)
 	romstage_handoff_init(wake_from_s3);
 
 	post_code(0x3f);
-	if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
-		tpm_setup(wake_from_s3);
 }

src/drivers/intel/fsp1_1/romstage.c

@@ -37,7 +37,6 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <security/tpm/tspi.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
@@ -167,15 +166,6 @@ void romstage_common(struct romstage_params *params)
 	if (romstage_handoff_init(
 			params->power_state->prev_sleep_state == ACPI_S3) < 0)
 		hard_reset();
-
-	/*
-	 * Initialize the TPM, unless the TPM was already initialized
-	 * in verstage and used to verify romstage.
-	 */
-	if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) &&
-	    !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
-		tpm_setup(params->power_state->prev_sleep_state ==
-			 ACPI_S3);
 }
 
 void after_cache_as_ram_stage(void)

src/drivers/tpm/Kconfig

@@ -0,0 +1,7 @@
+config TPM_INIT
+	bool
+	default y if TPM1 || TPM2
+	depends on !VBOOT
+	help
+	  This driver automatically initializes the TPM if vboot is not used.
+	  The TPM driver init is done during the ramstage chip init phase.

src/drivers/tpm/Makefile.inc

@@ -0,0 +1 @@
+ramstage-$(CONFIG_TPM_INIT) += tpm.c

src/drivers/tpm/tpm.c

@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Facebook Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <stddef.h>
+#include <bootstate.h>
+#include <security/tpm/tspi.h>
+
+#if IS_ENABLED(CONFIG_ARCH_X86)
+#include <arch/acpi.h>
+#endif
+
+static void init_tpm_dev(void *unused)
+{
+#if IS_ENABLED(CONFIG_ARCH_X86)
+	int s3resume = acpi_is_wakeup_s3();
+	tpm_setup(s3resume);
+#else
+	tpm_setup(false);
+#endif
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL);

src/mainboard/asus/kgpe-d16/romstage.c

@@ -46,7 +46,6 @@
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
 #include <arch/early_variables.h>
 #include <cbmem.h>
-#include <security/tpm/tspi.h>
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
@@ -624,9 +623,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);
 	pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
 	pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
-
-	if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
-		tpm_setup(s3resume);
 }
 
 /**

src/mainboard/google/link/romstage.c

@@ -35,7 +35,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include <security/tpm/tspi.h>
 #include <cbfs.h>
 
 #include <southbridge/intel/bd82x6x/chip.h>

src/mainboard/google/parrot/romstage.c

@@ -35,7 +35,6 @@
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <cbfs.h>
-#include <security/tpm/tspi.h>
 #include "ec/compal/ene932/ec.h"
 
 void pch_enable_lpc(void)

src/mainboard/google/rotor/Kconfig

@@ -20,8 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOC_MARVELL_MVMAP2315
 	select MAINBOARD_HAS_CHROMEOS
 	select BOARD_ROMSIZE_KB_4096
-	select MAINBOARD_HAS_I2C_TPM_GENERIC
-	select MAINBOARD_HAS_TPM1
 
 config VBOOT
 	select VBOOT_MOCK_SECDATA

src/mainboard/google/stout/romstage.c

@@ -35,7 +35,6 @@
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <bootmode.h>
-#include <security/tpm/tspi.h>
 #include <cbfs.h>
 #include <ec/quanta/it8518/ec.h>
 #include "ec.h"

src/mainboard/google/urara/Kconfig

@@ -24,8 +24,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_IMGTEC_PISTACHIO
 	select COMMON_CBFS_SPI_WRAPPER
 	select SPI_FLASH
-	select MAINBOARD_HAS_I2C_TPM_GENERIC
-	select MAINBOARD_HAS_TPM1
 
 config MAINBOARD_DIR
 	string

src/mainboard/intel/emeraldlake2/romstage.c

@@ -35,7 +35,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include <security/tpm/tspi.h>
 
 #define SIO_PORT 0x164e
 

src/mainboard/lenovo/x201/romstage.c

@@ -35,7 +35,6 @@
 #include <timestamp.h>
 #include <arch/acpi.h>
 #include <cbmem.h>
-#include <security/tpm/tspi.h>
 
 #include "dock.h"
 #include "arch/early_variables.h"
@@ -282,7 +281,4 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	if (!s3resume)
 		quick_ram_check();
-
-	if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
-		tpm_setup(s3resume);
 }

src/mainboard/pcengines/apu2/romstage.c

@@ -33,7 +33,6 @@
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <Fch/Fch.h>
-#include <security/tpm/tspi.h>
 
 #include "gpio_ftns.h"
 
@@ -103,9 +102,6 @@ void agesa_postcar(struct sysinfo *cb)
 	post_code(0x41);
 	AGESAWRAPPER(amdinitenv);
 
-	if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
-		tpm_setup(false);
-
 	outb(0xEA, 0xCD6);
 	outb(0x1, 0xcd7);
 }

src/mainboard/samsung/lumpy/romstage.c

@@ -28,7 +28,6 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <bootmode.h>
-#include <security/tpm/tspi.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>

src/mainboard/samsung/stumpy/romstage.c

@@ -37,7 +37,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include <security/tpm/tspi.h>
 #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif

src/northbridge/intel/sandybridge/romstage.c

@@ -28,7 +28,6 @@
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <halt.h>
-#include <security/tpm/tspi.h>
 #include <northbridge/intel/sandybridge/chip.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
@@ -117,8 +116,5 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	northbridge_romstage_finalize(s3resume);
 
-	if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
-		tpm_setup(s3resume);
-
 	post_code(0x3f);
 }

src/soc/intel/baytrail/romstage/romstage.c

@@ -30,7 +30,6 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <security/tpm/tspi.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
@@ -228,9 +227,6 @@ void romstage_common(struct romstage_params *params)
 	timestamp_add_now(TS_AFTER_INITRAM);
 
 	romstage_handoff_init(prev_sleep_state == ACPI_S3);
-
-	if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
-		tpm_setup(prev_sleep_state == ACPI_S3);
 }
 
 void asmlinkage romstage_after_car(void)

src/soc/intel/braswell/romstage/romstage.c

@@ -43,7 +43,6 @@
 #include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/spi.h>
-#include <security/tpm/tspi.h>
 
 void program_base_addresses(void)
 {

src/soc/intel/broadwell/romstage/romstage.c

@@ -26,7 +26,6 @@
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #include <elog.h>
-#include <security/tpm/tspi.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <stage_cache.h>
@@ -110,9 +109,6 @@ void romstage_common(struct romstage_params *params)
 	timestamp_add_now(TS_AFTER_INITRAM);
 
 	romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);
-
-	if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
-		tpm_setup(params->power_state->prev_sleep_state == ACPI_S3);
 }
 
 asmlinkage void romstage_after_car(void)