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nb/amd/mct_ddr3: Properly set MR0 WR value 

The existing code accidentally truncated the MSB from the MR0
WR value.  While this probably had a minimal effect in reality,
it should be configured correctly for maximal system stability.

Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13147
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Timothy Pearson 2015-11-24 14:11:52 -06:00 committed by Martin Roth
parent ad9a2bb0de
commit db84a99011
1 changed files with 1 additions and 1 deletions
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src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
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@ -967,7 +967,7 @@ static u32 mct_MR0(struct MCTStatStruc *pMCTstat,
/* Load data into MRS word */
ret |= (ppd & 0x1) << 12;
ret |= (wr_ap & 0x3) << 9;
ret |= (wr_ap & 0x7) << 9;
ret |= (dll_reset & 0x1) << 8;
ret |= (test_mode & 0x1) << 7;
ret |= ((cas_latency & 0xe) >> 1) << 4;