From db85b096d454576e2d75ea5976b86c4460517d0e Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 15 Oct 2021 13:37:47 -0700 Subject: [PATCH] mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz Update board type to 4 as per MRC team's input. This fixes LP5 sagv point 3 being clipped from the expected 5200Mhz to 4800Mhz. TEST=Boot to OS, verify frequency locked. Signed-off-by: Bora Guvendik Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373 Tested-by: build bot (Jenkins) Reviewed-by: Selma Bensaid Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/adlrvp/memory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 93f1aa3a25..f4ae5416d5 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -227,7 +227,7 @@ static const struct mb_cfg adlm_lp4_mem_config = { .LpDdrDqDqsReTraining = 1, - .UserBd = BOARD_TYPE_ULT_ULX, + .UserBd = BOARD_TYPE_ULT_ULX_T4, }; static const struct mb_cfg adlm_lp5_mem_config = { @@ -283,7 +283,7 @@ static const struct mb_cfg adlm_lp5_mem_config = { .ect = false, /* Early Command Training */ - .UserBd = BOARD_TYPE_ULT_ULX, + .UserBd = BOARD_TYPE_ULT_ULX_T4, .lp5x_config = { .ccc_config = 0xff,