From db86a35ab686937fc4e4eb9a4f7417595bd9b519 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 14 Jun 2019 18:54:32 +0200 Subject: [PATCH] mb/ocp/wedge100s: Use the new IPMI driver * Enable decoding the IPMI KCS to LPC * Select the IPMI driver * Add the PNP device that holds the IPMI KCS base address Tested on Wedge100s. Change-Id: I35634bbcbe6893bd72ec7e41f6ca7bba09d819a2 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/33489 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/ocp/wedge100s/Kconfig | 1 + src/mainboard/ocp/wedge100s/devicetree.cb | 3 +++ src/mainboard/ocp/wedge100s/romstage.c | 4 ++++ 3 files changed, 8 insertions(+) diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index bd5e6655af..491829a084 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM1 select DRIVERS_UART_8250IO select SUPERIO_ITE_IT8528E + select IPMI_KCS config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb index 48410bae08..3552a6db1b 100644 --- a/src/mainboard/ocp/wedge100s/devicetree.cb +++ b/src/mainboard/ocp/wedge100s/devicetree.cb @@ -60,6 +60,9 @@ chip soc/intel/fsp_broadwell_de device pnp 6e.18 off end device pnp 6e.19 off end end #superio/ite/it8528e + chip drivers/ipmi + device pnp ca2.0 on end # IPMI KCS + end end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index 7fdc981915..108d7a1c4d 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -38,6 +38,10 @@ void early_mainboard_romstage_entry(void) pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, (0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1); + /* Decode IPMI KCS */ + pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, + (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1); + if (CONFIG(CONSOLE_SERIAL)) ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);