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soc/intel/cannonlake: Add PCH series check for CML LP PCH

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TEST=Verify PM_STS1 value is is not 0xFF.

Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31434
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maulik V Vaghela 2019-02-15 11:55:20 +05:30 committed by Subrata Banik
parent ba8af5807c
commit db9e9ac30d
1 changed files with 13 additions and 7 deletions
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20
src/soc/intel/cannonlake/lpc.c
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@ -70,19 +70,25 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
uint8_t get_pch_series(void)
{
uint16_t lpc_did_hi_byte;
uint8_t pch_series = PCH_UNKNOWN_SERIES;
/*
* Fetch upper 8 bits on LPC device ID to determine PCH type
* Adding 1 to the offset to fetch upper 8 bits
*/
lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);
if (lpc_did_hi_byte == 0x9D)
return PCH_LP;
else if (lpc_did_hi_byte == 0xA3)
return PCH_H;
else
return PCH_UNKNOWN_SERIES;
switch (lpc_did_hi_byte) {
case 0x9D: /* CNL-LP */
case 0x02: /* CML-LP */
pch_series = PCH_LP;
break;
case 0xA3:
pch_series = PCH_H;
break;
default:
break;
}
return pch_series;
}
#if ENV_RAMSTAGE