soc/amd/common/psp: Move early init to soc
The initialization code in common//psp is very specific to Family 15h. Move this to the stoneyridge directory. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020365 Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Felix Held
Felix Held
parent
737e56aa56
commit
dba3229b90
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@ -15,24 +15,8 @@
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#ifndef __AMD_PSP_H__
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#define __AMD_PSP_H__
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#include <amdblocks/agesawrapper.h>
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#include <soc/pci_devs.h>
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#include <types.h>
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/* Extra, Special Purpose Registers in the PSP PCI Config Space */
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/* PSP Mirror Features Capabilities and Control Register */
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#define PSP_PCI_MIRRORCTRL1_REG 0x44 /* PSP Mirror Ctrl Reg */
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#define PMNXTPTRW_MASK 0xff /* PCI AFCR pointer mask */
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#define PMNXTPTRW_EXPOSE 0xa4 /* Pointer to expose the AFCR */
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#define PSP_PCI_EXT_HDR_CTRL 0x48 /* Extra PCI Header Ctrl */
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#define MAGIC_ENABLES 0x34 /* Extra PCI HDR Ctl Enables */
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#define PSP_MAILBOX_BASE 0x70 /* Mailbox offset from PCIe BAR */
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#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
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#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
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/* Get the mailbox base address - specific to family of device. */
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struct psp_mbox *soc_get_mbox_address(void);
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/* x86 to PSP commands */
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#define MBOX_BIOS_CMD_DRAM_INFO 0x01
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@ -1,3 +1,4 @@
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bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
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romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
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@ -33,73 +33,6 @@ static const char *psp_status_init_timeout = "error: PSP init timeout";
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static const char *psp_status_cmd_timeout = "error: PSP command timeout";
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static const char *psp_status_noerror = "";
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static void psp_bar_init_early(void)
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{
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u32 psp_mmio_size;
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u32 value32;
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u32 base, limit;
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/* Check for presence of the PSP */
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if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: SOC_PSP_DEV device not found at D%xF%x\n",
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PSP_DEV, PSP_FUNC);
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return;
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}
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/* Check if PSP BAR has been assigned, and if so, just return */
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if (pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) &
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~PCI_BASE_ADDRESS_MEM_ATTR_MASK)
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return;
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/* Otherwise, do an early init of the BAR */
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pci_write_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4, 0xffffffff);
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psp_mmio_size = ~pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) + 1;
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printk(BIOS_SPEW, "PSP: BAR size is 0x%x\n", psp_mmio_size);
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/* Assign BAR to an initial temporarily defined region */
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pci_write_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4,
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PSP_MAILBOX_BAR3_BASE);
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/* Route MMIO through the northbridge */
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pci_write_config32(SOC_PSP_DEV, PCI_COMMAND,
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(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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limit = ((PSP_MAILBOX_BAR3_BASE + psp_mmio_size - 1) >> 8) & ~0xff;
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pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(7), limit);
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base = (PSP_MAILBOX_BAR3_BASE >> 8) | MMIO_WE | MMIO_RE;
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pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(7), base);
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pci_write_config32(SOC_PSP_DEV, PSP_PCI_EXT_HDR_CTRL, MAGIC_ENABLES);
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/* Update the capability chain */
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value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG);
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value32 &= ~PMNXTPTRW_MASK;
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value32 |= PMNXTPTRW_EXPOSE;
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pci_write_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG, value32);
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}
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static uintptr_t get_psp_bar3_addr(void)
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{
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uintptr_t psp_mmio;
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/* Check for presence of the PSP */
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if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n",
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PSP_DEV, PSP_FUNC);
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return 0;
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}
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/* D8F0x48[12] is the Bar3Hide flag, check it */
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if (pci_read_config32(SOC_PSP_DEV, PSP_PCI_EXT_HDR_CTRL) & BAR3HIDE) {
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psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
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if (psp_mmio == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n");
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return 0;
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}
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return psp_mmio;
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} else {
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return pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) &
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~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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}
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}
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static const char *status_to_string(int err)
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{
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switch (err) {
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@ -120,23 +53,6 @@ static const char *status_to_string(int err)
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}
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}
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static struct psp_mbox *get_mbox_address(void)
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{
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uintptr_t baseptr;
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baseptr = get_psp_bar3_addr();
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if (baseptr == 0) {
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psp_bar_init_early();
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baseptr = get_psp_bar3_addr();
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if (baseptr == 0) {
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printk(BIOS_WARNING, "PSP: %s(), psp_bar_init_early() failed...\n",
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__func__);
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return NULL;
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}
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}
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return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE);
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}
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static u32 rd_mbox_sts(struct psp_mbox *mbox)
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{
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return read32(&mbox->mbox_status);
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@ -192,7 +108,7 @@ static int wait_command(struct psp_mbox *mbox)
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static int send_psp_command(u32 command, void *buffer)
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{
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struct psp_mbox *mbox = get_mbox_address();
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struct psp_mbox *mbox = soc_get_mbox_address();
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if (!mbox)
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return -PSPSTS_NOBASE;
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@ -59,6 +59,7 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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romstage-y += tsc_freq.c
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romstage-y += southbridge.c
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romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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romstage-y += psp.c
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verstage-y += gpio.c
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verstage-y += i2c.c
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@ -93,6 +94,7 @@ ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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ramstage-y += usb.c
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ramstage-y += tsc_freq.c
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ramstage-y += finalize.c
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ramstage-y += psp.c
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all-y += reset.c
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@ -102,6 +104,7 @@ smm-y += smi_util.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_DEBUG_SMI) += uart.c
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smm-y += gpio.c
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smm-y += psp.c
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CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
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CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include
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@ -290,10 +290,17 @@
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#define SPI_RD4DW_EN_HOST BIT(15)
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/* Platform Security Processor D8F0 */
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void soc_enable_psp_early(void);
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#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
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#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */
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#define PSP_BAR_ENABLES 0x48
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#define PSP_MAILBOX_BAR_EN 0x10
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#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
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#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
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/* IO 0xcf9 - Reset control port*/
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#define FULL_RST BIT(3)
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#define RST_CMD BIT(2)
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@ -0,0 +1,58 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/northbridge.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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void soc_enable_psp_early(void)
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{
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u32 base, limit, cmd;
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/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
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base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
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limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
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/* Preload a value into BAR and enable it */
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pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
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pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
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/* Enable memory access and master */
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cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
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};
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struct psp_mbox *soc_get_mbox_address(void)
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{
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uintptr_t psp_mmio;
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/* Check for presence of the PSP */
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if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n",
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PSP_DEV, PSP_FUNC);
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return 0;
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}
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/* Determine if Bar3Hide has been set, and if hidden get the base from
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* the MSR instead. */
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if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
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psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
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if (psp_mmio == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n");
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return 0;
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}
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} else {
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psp_mmio = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) &
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~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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}
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return (struct psp_mbox *)(psp_mmio + PSP_MAILBOX_OFFSET);
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}
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@ -31,6 +31,7 @@
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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@ -42,28 +43,6 @@ void __weak mainboard_romstage_entry_s3(int s3_resume)
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/* By default, don't do anything */
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}
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static void load_smu_fw1(void)
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{
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u32 base, limit, cmd;
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/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
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base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
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limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
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/* Preload a value into "BAR3" and enable it */
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pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
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pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
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/* Enable memory access and master */
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cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
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psp_load_named_blob(BLOB_SMU_FW, "smu_fw");
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}
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static void agesa_call(void)
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{
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post_code(0x37);
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@ -92,8 +71,9 @@ asmlinkage void car_stage_entry(void)
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console_init();
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soc_enable_psp_early();
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if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
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load_smu_fw1();
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psp_load_named_blob(BLOB_SMU_FW, "smu_fw");
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mainboard_romstage_entry_s3(s3_resume);
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elog_boot_notify(s3_resume);
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