- sc520 updates. move PAR setup to mainboard auto.c
- some ts5300 code. Let's push this upstream for now. - fix a typo in device.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
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@ -83,11 +83,15 @@ setupsc520(void){
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sp = (unsigned short *)0xfffef040;
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*sp = 0;
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// moved to auto.c by stepan
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setup_pars();
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#if 0
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/* as per the book: */
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/* PAR register setup */
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/* set up the PAR registers as they are on the MSM586SEG */
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par = (unsigned long *) 0xfffef088;
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/* NOTE: move this to mainboard.c ASAP */
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#if 1
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@ -111,7 +115,7 @@ setupsc520(void){
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par += 15;
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#endif
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*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
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#endif
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/* CPCSF register */
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@ -684,7 +684,7 @@ void dev_configure(void)
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*/
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void dev_enable(void)
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{
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printk_info("Enabling resourcess...\n");
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printk_info("Enabling resources...\n");
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/* now enable everything. */
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enable_resources(&dev_root);
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@ -12,6 +12,34 @@
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#include "ram/ramtest.c"
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#include "cpu/x86/bist.h"
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//#include "lib/delay.c"
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void setup_pars(void)
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{
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volatile unsigned long *par;
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/* as per the book: */
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/* PAR register setup */
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/* set up the PAR registers as they are on the MSM586SEG */
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par = (unsigned long *) 0xfffef088;
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/* NOTE: move this to mainboard.c ASAP */
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*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
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*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
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*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
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*par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
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*par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
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*par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
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*par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
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*par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
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*par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
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*par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
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*par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
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*par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
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*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
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*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
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*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
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*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
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}
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#include "cpu/amd/sc520/raminit.c"
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typedef void (*lj)(void);
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@ -161,6 +189,8 @@ static inline void irqinit(void){
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#endif
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}
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static void main(unsigned long bist)
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{
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volatile int i;
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@ -2,7 +2,7 @@
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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default ROM_SIZE = 512 * 1024
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default ROM_SIZE = 128 * 1024
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default FALLBACK_SIZE = 0x10000
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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@ -134,13 +134,13 @@ chip cpu/amd/sc520
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device pci_domain 0 on
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device pci 0.0 on end
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chip drivers/pci/onboard
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device pci 12.0 on end # enet
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end
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chip drivers/pci/onboard
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device pci 14.0 on end # 69000
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register "rom_address" = "0x2000000"
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end
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# chip drivers/pci/onboard
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# device pci 12.0 on end # enet
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# end
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# chip drivers/pci/onboard
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# device pci 14.0 on end # 69000
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# register "rom_address" = "0x2000000"
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# end
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# register "com1" = "{1}"
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# register "com1" = "{1, 0, 0x3f8, 4}"
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end
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@ -33,6 +33,10 @@ uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_CONSOLE_SERIAL8250
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@ -48,6 +52,24 @@ uses CONFIG_PCI_ROM_RUN
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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#default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x2f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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default DEFAULT_CONSOLE_LOGLEVEL=9
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default MAXIMUM_CONSOLE_LOGLEVEL=9
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## ROM_SIZE is the size of boot ROM that this board will use.
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@ -12,39 +12,46 @@
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#include "ram/ramtest.c"
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#include "cpu/x86/bist.h"
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//#include "lib/delay.c"
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void setup_pars(void)
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{
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volatile unsigned long *par;
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/* as per the book: */
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/* PAR register setup */
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/* set up the PAR registers as they are on the MSM586SEG */
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par = (unsigned long *) 0xfffef088;
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/* NOTE: move this to mainboard.c ASAP */
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*par++ = 0x00000000;
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*par++ = 0x340f0070;
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*par++ = 0x380701f0;
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*par++ = 0x3c0103f6;
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*par++ = 0x2c0f0300;
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*par++ = 0x447c00a0;
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*par++ = 0xe600000c;
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*par++ = 0x300046e8;
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*par++ = 0x500400d0;
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*par++ = 0x281f0140;
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*par++ = 0x00000000;
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*par++ = 0x00000000;
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*par++ = 0x00000000;
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*par++ = 0x8a07c940;
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*par++ = 0x00000000;
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*par++ = 0xee00400e;
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}
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#include "cpu/amd/sc520/raminit.c"
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struct mem_controller {
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int i;
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};
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#include "debug.c"
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static void hard_reset(void)
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{
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print_err("Hard reset called.\n");
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while (1) ;
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}
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static void memreset_setup(void)
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static inline void dumpmem(void)
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{
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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// return smbus_read_byte(device, address);
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}
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//#include "sdram/generic_sdram.c"
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static inline void dumpmem(void){
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int i, j;
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unsigned char *l;
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unsigned char c;
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@ -163,27 +170,26 @@ static void main(unsigned long bist)
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for(i = 0; i < 100; i++)
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;
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setupsc520();
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irqinit();
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uart_init();
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console_init();
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for(i = 0; i < 100; i++)
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print_err("fill usart\r\n");
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// while(1)
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print_err("HI THERE!\r\n");
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// sizemem();
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//for(i = 0; i < 100; i++)
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// print_err("fill usart\r\n");
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print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\r\n");
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staticmem();
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print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60);
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print_err("\n");
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// while(1)
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print_err("STATIC MEM DONE\r\n");
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outb(0xee, 0x80);
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print_err("loop forever ...\n");
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// sw ctimer millisecond count
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//print_err("\r\nc60 is "); print_err_hex16(*(unsigned short *)0xfffefc60);
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//print_err("\r\n");
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print_err("Memory initialized: 32MB\r\n");
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#if 0
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#if 1
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/* clear memory 1meg */
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__asm__ volatile(
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// Check 32MB of memory @ 0
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ram_check(0x00000000, 0x02000000);
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#endif
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#if 1
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/* Don't think this is needed for the ts5300.
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* The MMCRs are at fffef000 and the image is only 64k (without
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* payload) so it fits exactly between MMCR and 4G
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*/
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#if 0
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{
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volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000;
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volatile unsigned char *dst = (unsigned char *) 0x4000;
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@ -39,108 +39,115 @@ static void enable_dev(struct device *dev) {
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volatile struct mmcrpic *pic = MMCRPIC;
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volatile struct mmcr *mmcr = MMCRDEFAULT;
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/* ts5300 has this register set to a weird value.
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* follow the board, not the manual!
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*/
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/* currently, nothing in the device to use, so ignore it. */
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printk_err("Technologic Systems 5300 ENTER %s\n", __FUNCTION__);
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/* from fuctory bios */
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/* NOTE: the following interrupt settings made interrupts work
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* for hard drive, and serial, but not for ethernet
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*/
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printk_err("Setting up PIC\n");
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/* just do what they say and nobody gets hurt. */
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mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE;
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mmcr->pic.pcicr = 0 ;
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/* all ints to level */
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mmcr->pic.mpicmode = 0;
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mmcr->pic.sl1picmode = 0;
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mmcr->pic.sl2picmode = 0x80;
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mmcr->pic.sl2picmode = 0;
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mmcr->pic.intpinpol = 0;
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mmcr->pic.intpinpol = 0x100;
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mmcr->pic.pit0map = 1;
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mmcr->pic.uart1map = 0xc;
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mmcr->pic.uart2map = 0xb;
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mmcr->pic.rtcmap = 3;
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mmcr->pic.ferrmap = 8;
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mmcr->pic.gp0imap = 6;
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mmcr->pic.gp1imap = 2;
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mmcr->pic.gp2imap = 7;
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mmcr->pic.uart1map = 0x0c;
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mmcr->pic.uart2map = 0x0b;
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mmcr->pic.rtcmap = 0x03;
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mmcr->pic.ferrmap = 0x00;
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mmcr->pic.intpinpol = 0x100;
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mmcr->pic.gp0imap = 0x00;
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mmcr->pic.gp1imap = 0x02;
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mmcr->pic.gp2imap = 0x07;
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mmcr->pic.gp3imap = 0x05;
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mmcr->pic.gp4imap = 0x06;
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mmcr->pic.gp5imap = 0x0d;
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mmcr->pic.gp6imap = 0x15;
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mmcr->pic.gp7imap = 0x16;
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mmcr->pic.gp10imap = 0x9;
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mmcr->pic.gp8imap = 0x3;
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mmcr->pic.gp9imap = 0x4;
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mmcr->pic.gp10imap = 0x9;
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// irqdump();
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printk_err("Setting up sysarb\n");
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mmcr->dbctl.dbctl = 0x01;
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mmcr->sysarb.ctl = 0x00;
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mmcr->sysarb.menb = 0x1f;
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mmcr->sysarb.prictl = 0x40000f0f;
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irqdump();
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printk_err("uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
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printk_err("0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
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printk_err("0xc22 0x%x\n", *(unsigned short *) 0xfffefc22b);
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/* The following block has NOT proven sufficient to get
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* the VGA hardware to talk to us
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*/
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/* let's set some mmcr stuff per the BIOS settings */
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mmcr->dbctl.dbctl = 0x10;
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mmcr->sysarb.ctl = 6;
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mmcr->sysarb.menb = 0xf;
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mmcr->sysarb.prictl = 0xc0000f0f;
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/* this is bios setting, depends on sysarb above */
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mmcr->hostbridge.ctl = 0x108;
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printk_err("TS5300 EXIT %s\n", __FUNCTION__);
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mmcr->hostbridge.ctl = 0x0;
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mmcr->hostbridge.tgtirqctl = 0x0;
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mmcr->hostbridge.tgtirqsta = 0xf00;
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mmcr->hostbridge.mstirqctl = 0x0;
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mmcr->hostbridge.mstirqsta = 0x708;
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printk_err("Setting up pio\n");
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/* pio */
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mmcr->pio.data31_16 = 0xffbf;
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mmcr->pio.pfs15_0 = 0xffff;
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mmcr->pio.pfs31_16 = 0xffff;
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mmcr->pio.cspfs = 0xfe;
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mmcr->pio.clksel = 0x13;
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mmcr->pio.dsctl = 0x200;
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mmcr->pio.data15_0 = 0xde04;
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mmcr->pio.data31_16 = 0xef9f;
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/* pci stuff */
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mmcr->pic.pciintamap = 0xa;
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printk_err("Setting up sysmap\n");
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/* system memory map */
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mmcr->sysmap.adddecctl = 0x04;
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mmcr->sysmap.wpvsta = 0x8006;
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mmcr->sysmap.par[1] = 0x340f0070;
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mmcr->sysmap.par[2] = 0x380701f0;
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mmcr->sysmap.par[3] = 0x3c0103f6;
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mmcr->sysmap.par[4] = 0x2c0f0300;
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mmcr->sysmap.par[5] = 0x447c00a0;
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mmcr->sysmap.par[6] = 0xe600000c;
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mmcr->sysmap.par[7] = 0x300046e8;
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mmcr->sysmap.par[8] = 0x500400d0;
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mmcr->sysmap.par[9] = 0x281f0140;
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mmcr->sysmap.par[13] = 0x8a07c940;
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mmcr->sysmap.par[15] = 0xee00400e;
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/* END block where vga hardware still will not talk to us */
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/* all we get from VGA I/O addresses are ffff etc.
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*/
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mmcr->sysmap.adddecctl = 0x10;
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printk_err("Setting up gpctl\n");
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mmcr->gpctl.gpcsrt = 0x01;
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mmcr->gpctl.gpcspw = 0x09;
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mmcr->gpctl.gpcsoff = 0x01;
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mmcr->gpctl.gprdw = 0x07;
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mmcr->gpctl.gprdoff = 0x02;
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mmcr->gpctl.gpwrw = 0x07;
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mmcr->gpctl.gpwroff = 0x02;
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/* VGA now talks to us, so this adddecctl was the trick.
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* still no interrupts from enet.
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* Let's try fixing the piodata stuff, as there may be
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* some wire there not documented.
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*/
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mmcr->pio.data31_16 = 0xffbf;
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/* also, our sl?picmode needs to match fuctory bios */
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mmcr->pic.sl1picmode = 0x80;
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mmcr->pic.sl2picmode = 0x0;
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/* and, finally, they do set gp5imap and we don't.
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*/
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mmcr->pic.gp5imap = 0xd;
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/* remaining problem: almost certainly, the irq table is bogus
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* NO SHOCK as it came from fuctory bios.
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* but let's try these 4 changes for now and see what shakes.
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*/
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/* still not interrupts. */
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//mmcr->reset.sysinfo = 0xdf;
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//mmcr->reset.rescfg = 0x5;
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/* their IRQ table is wrong. Just hardwire it */
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{
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char pciints[4] = {15, 15, 15, 15};
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pci_assign_irqs(0, 12, pciints);
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}
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//{
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// char pciints[4] = {15, 15, 15, 15};
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// pci_assign_irqs(0, 12, pciints);
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//}
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/* the assigned failed but we just noticed -- there is no
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* dma mapping, and selftest on e100 requires that dma work
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*/
|
||||
/* follow fuctory here */
|
||||
mmcr->dmacontrol.extchanmapa = 0x3210;
|
||||
mmcr->dmacontrol.extchanmapa = 0xf210;
|
||||
mmcr->dmacontrol.extchanmapb = 0xffff;
|
||||
|
||||
/* hack for IDIOTIC need to fix rom_start */
|
||||
printk_err("Patching rom_start due to sc520 limits\n");
|
||||
rom_start = 0x2000000 + 0x40000;
|
||||
rom_start = 0x09400000 + 0xe0000;
|
||||
rom_end = rom_start + PAYLOAD_SIZE - 1;
|
||||
|
||||
printk_err("TS5300 EXIT %s\n", __FUNCTION__);
|
||||
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_technologic_ts5300_ops = {
|
||||
CHIP_NAME("Technologic Systems TS5300 mainboard ")
|
||||
.enable_dev = enable_dev
|
||||
|
|
Loading…
Reference in New Issue