soc/intel/tigerlake: Update FSP params for Jasper Lake

Update FSP parameters for various configurations like:
- graphics
- USB
- PCIe root ports
- SD card
- eMMC
- Audio
- Basic UART configuration

These are the initial settings for JSL.

This patch also corrects the debug_interface_flag definitions.

TEST=Build dedede board

Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

src/soc/intel/tigerlake/chip.h

@@ -204,6 +204,15 @@ struct soc_intel_tigerlake_config {
 	 */
 	uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 
+	/* Debug interface selection */
+	enum {
+		DEBUG_INTERFACE_RAM = (1 << 0),
+		DEBUG_INTERFACE_UART = (1 << 1),
+		DEBUG_INTERFACE_USB3 = (1 << 3),
+		DEBUG_INTERFACE_SERIAL_IO = (1 << 4),
+		DEBUG_INTERFACE_TRACEHUB = (1 << 5),
+	} debug_interface_flag;
+
 	/* GPIO SD card detect pin */
 	unsigned int sdcard_cd_gpio;
 

src/soc/intel/tigerlake/fsp_params_jsl.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -12,10 +12,19 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-
+#include <assert.h>
+#include <console/console.h>
 #include <fsp/api.h>
+#include <fsp/ppi/mp_service_ppi.h>
+#include <fsp/util.h>
 #include <intelblocks/lpss.h>
+#include <intelblocks/mp_init.h>
+#include <intelblocks/xdci.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/pci_devs.h>
 #include <soc/ramstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
 
 static const pci_devfn_t serial_io_dev[] = {
 	PCH_DEVFN_I2C0,
@@ -32,10 +41,138 @@ static const pci_devfn_t serial_io_dev[] = {
 	PCH_DEVFN_UART2
 };
 
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+	const struct soc_intel_tigerlake_config *config = config_of_soc();
+
+	/* LPSS controllers configuration */
+
+	/* I2C */
+	_Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >=
+			ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!");
+	memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode,
+		sizeof(config->SerialIoI2cMode));
+
+	/* GSPI */
+	_Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >=
+			ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!");
+	memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode,
+		sizeof(config->SerialIoGSpiMode));
+
+	_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >=
+			ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!");
+	memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode,
+		sizeof(config->SerialIoGSpiCsMode));
+
+	_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >=
+			ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!");
+	memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState,
+		sizeof(config->SerialIoGSpiCsState));
+
+	/* UART */
+	_Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >=
+			ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!");
+	memcpy(params->SerialIoUartMode, config->SerialIoUartMode,
+		sizeof(config->SerialIoUartMode));
+}
+
 /* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
-	/* TODO: Update with UPD override as FSP matures */
+	unsigned int i;
+	struct device *dev;
+	FSP_S_CONFIG *params = &supd->FspsConfig;
+	struct soc_intel_tigerlake_config *config = config_of_soc();
+
+	/* Parse device tree and fill in FSP UPDs */
+	parse_devicetree(params);
+
+	/* Load VBT before devicetree-specific config. */
+	params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+
+	/* Check if IGD is present and fill Graphics init param accordingly */
+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
+
+	if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
+		params->PeiGraphicsPeimInit = 1;
+	else
+		params->PeiGraphicsPeimInit = 0;
+
+	/* Use coreboot MP PPI services if Kconfig is enabled */
+	if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
+		params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+		params->SkipMpInit = 0;
+	} else {
+		params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+	}
+
+	/* Unlock upper 8 bytes of RTC RAM */
+	params->RtcMemoryLock = 0;
+
+	/* Legacy 8254 timer support */
+	params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+	params->Enable8254ClockGatingOnS3 = 1;
+
+	/* disable Legacy PME */
+	memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
+	/* USB configuration */
+	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+
+		params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+		params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+		params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+		params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
+		params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
+		params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+
+		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+		if (config->usb3_ports[i].tx_de_emp) {
+			params->Usb3HsioTxDeEmphEnable[i] = 1;
+			params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
+		}
+		if (config->usb3_ports[i].tx_downscale_amp) {
+			params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+			params->Usb3HsioTxDownscaleAmp[i] =
+				config->usb3_ports[i].tx_downscale_amp;
+		}
+	}
+
+	/* SDCard related configuration */
+	params->ScsSdCardEnabled = pcidev_path_on_root(PCH_DEVFN_SDCARD) ? dev->enabled : 0;
+
+	params->Device4Enable = config->Device4Enable;
+
+	/* eMMC configuration */
+	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
+	if (!dev) {
+		params->ScsEmmcEnabled = 0;
+	} else {
+		params->ScsEmmcEnabled = dev->enabled;
+		params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+	}
+
+	/* Enable xDCI controller if enabled in devicetree and allowed */
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
+	if (!dev || !xdci_can_enable())
+		dev->enabled = 0;
+	params->XdciEnable = dev->enabled;
+
+	/* Provide correct UART number for FSP debug logs */
+	params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+
+	/* Override/Fill FSP Silicon Param for mainboard */
+	mainboard_silicon_init_params(params);
+}
+
+/* Mainboard GPIO Configuration */
+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
 
 /* Return list of SOC LPSS controllers */

src/soc/intel/tigerlake/include/soc/pci_devs.h

@@ -86,6 +86,11 @@
 #define  PCH_DEV_SRAM		_PCH_DEV(XHCI, 2)
 #define  PCH_DEV_CNVI_WIFI	_PCH_DEV(XHCI, 3)
 
+#if CONFIG(SOC_INTEL_JASPERLAKE)
+#define  PCH_DEVFN_SDCARD	_PCH_DEVFN(XHCI, 5)
+#define  PCH_DEV_SDCARD		_PCH_DEV(XHCI, 5)
+#endif
+
 #define PCH_DEV_SLOT_SIO3	0x15
 #define  PCH_DEVFN_I2C0		_PCH_DEVFN(SIO3, 0)
 #define  PCH_DEVFN_I2C1		_PCH_DEVFN(SIO3, 1)
@@ -122,6 +127,12 @@
 #define  PCH_DEV_I2C5		_PCH_DEV(SIO4, 1)
 #define  PCH_DEV_UART2		_PCH_DEV(SIO4, 2)
 
+#if CONFIG(SOC_INTEL_JASPERLAKE)
+#define PCH_DEV_SLOT_STORAGE	0x1a
+#define  PCH_DEVFN_EMMC		_PCH_DEVFN(STORAGE, 0)
+#define  PCH_DEV_EMMC		_PCH_DEV(STORAGE, 0)
+#endif
+
 #define PCH_DEV_SLOT_PCIE	0x1c
 #define  PCH_DEVFN_PCIE1	_PCH_DEVFN(PCIE, 0)
 #define  PCH_DEVFN_PCIE2	_PCH_DEVFN(PCIE, 1)

src/soc/intel/tigerlake/romstage/fsp_params_jsl.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2019-2020 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,10 +13,113 @@
  * GNU General Public License for more details.
  */
 
+#include <assert.h>
+#include <console/console.h>
 #include <fsp/util.h>
+#include <soc/pci_devs.h>
 #include <soc/romstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
+		const struct soc_intel_tigerlake_config *config)
+{
+	unsigned int i;
+	const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	uint32_t mask = 0;
+
+	if (!dev || !dev->enabled) {
+		/* Skip IGD initialization in FSP if device is disabled in devicetree.cb */
+		m_cfg->InternalGfx = 0;
+		m_cfg->IgdDvmt50PreAlloc = 0;
+	} else {
+		m_cfg->InternalGfx = 1;
+		/* Set IGD stolen size to 60MB. */
+		m_cfg->IgdDvmt50PreAlloc = 0xFE;
+	}
+
+	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+	m_cfg->SaGv = config->SaGv;
+	m_cfg->RMT = config->RMT;
+
+	/* PCIe root port configuration */
+	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+		if (config->PcieRpEnable[i])
+			mask |= (1 << i);
+	}
+
+	m_cfg->PcieRpEnableMask = mask;
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcUsage) >=
+			ARRAY_SIZE(config->PcieClkSrcUsage), "copy buffer overflow!");
+	memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
+			sizeof(config->PcieClkSrcUsage));
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcClkReq) >=
+			ARRAY_SIZE(config->PcieClkSrcClkReq), "copy buffer overflow!");
+	memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+			sizeof(config->PcieClkSrcClkReq));
+
+	m_cfg->PrmrrSize = config->PrmrrSize;
+	m_cfg->EnableC6Dram = config->enable_c6dram;
+
+	/* Disable BIOS Guard */
+	m_cfg->BiosGuard = 0;
+
+	/* Set CPU Ratio */
+	m_cfg->CpuRatio = 0;
+	m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
+			DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB;
+
+	/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
+	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+
+
+	/* Enable SMBus controller based on config */
+	m_cfg->SmbusEnable = config->SmbusEnable;
+
+	/* Set debug probe type */
+	m_cfg->PlatformDebugConsent = config->DebugConsent;
+
+	/* VT-d config */
+	m_cfg->VtdDisable = 0;
+
+	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+
+	/* Audio */
+	m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0;
+
+	m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
+	m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkDmicEnable) >=
+			ARRAY_SIZE(config->PchHdaAudioLinkDmicEnable), "copy buffer overflow!");
+	memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
+		sizeof(config->PchHdaAudioLinkDmicEnable));
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSspEnable) >=
+			ARRAY_SIZE(config->PchHdaAudioLinkSspEnable), "copy buffer overflow!");
+	memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
+		sizeof(config->PchHdaAudioLinkSspEnable));
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSndwEnable) >=
+			ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!");
+	memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
+		sizeof(config->PchHdaAudioLinkSndwEnable));
+}
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	/* TODO: Update with UPD override as FSP matures */
+	const struct soc_intel_tigerlake_config *config = config_of_soc();
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	soc_memory_init_params(m_cfg, config);
+
+	mainboard_memory_init_params(mupd);
+}
+
+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }

src/soc/intel/tigerlake/romstage/fsp_params_tgl.c

@@ -23,15 +23,6 @@
 #include <soc/soc_chip.h>
 #include <string.h>
 
-/* Debug interface flag */
-enum debug_interface_flag {
-	DEBUG_INTERFACE_RAM  = 0x1,
-	DEBUG_INTERFACE_UART = 0x2,
-	DEBUG_INTERFACE_USB3 = 0x4,
-	DEBUG_INTERFACE_SERIAL_IO  = 0x8,
-	DEBUG_INTERFACE_TRACEHUB = 0x10
-};
-
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_tigerlake_config *config)
 {