soc/intel/tigerlake: Update FSP params for Jasper Lake
Update FSP parameters for various configurations like: - graphics - USB - PCIe root ports - SD card - eMMC - Audio - Basic UART configuration These are the initial settings for JSL. This patch also corrects the debug_interface_flag definitions. TEST=Build dedede board Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Maulik V Vaghela
Subrata Banik
parent
de36d7ebfa
commit
dba6c4cfc0
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@ -204,6 +204,15 @@ struct soc_intel_tigerlake_config {
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*/
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uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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/* Debug interface selection */
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enum {
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DEBUG_INTERFACE_RAM = (1 << 0),
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DEBUG_INTERFACE_UART = (1 << 1),
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DEBUG_INTERFACE_USB3 = (1 << 3),
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DEBUG_INTERFACE_SERIAL_IO = (1 << 4),
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DEBUG_INTERFACE_TRACEHUB = (1 << 5),
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} debug_interface_flag;
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/* GPIO SD card detect pin */
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unsigned int sdcard_cd_gpio;
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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* Copyright (C) 2019-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -12,10 +12,19 @@
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <fsp/api.h>
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#include <fsp/ppi/mp_service_ppi.h>
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#include <fsp/util.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/xdci.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_I2C0,
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@ -32,10 +41,138 @@ static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_UART2
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};
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static void parse_devicetree(FSP_S_CONFIG *params)
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{
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const struct soc_intel_tigerlake_config *config = config_of_soc();
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/* LPSS controllers configuration */
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/* I2C */
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_Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >=
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ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!");
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memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode,
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sizeof(config->SerialIoI2cMode));
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/* GSPI */
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_Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >=
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ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!");
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memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode,
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sizeof(config->SerialIoGSpiMode));
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_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >=
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ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!");
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memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode,
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sizeof(config->SerialIoGSpiCsMode));
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_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >=
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ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!");
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memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState,
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sizeof(config->SerialIoGSpiCsState));
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/* UART */
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_Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >=
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ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!");
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memcpy(params->SerialIoUartMode, config->SerialIoUartMode,
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sizeof(config->SerialIoUartMode));
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}
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/* UPD parameters to be initialized before SiliconInit */
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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/* TODO: Update with UPD override as FSP matures */
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unsigned int i;
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struct device *dev;
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FSP_S_CONFIG *params = &supd->FspsConfig;
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struct soc_intel_tigerlake_config *config = config_of_soc();
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/* Parse device tree and fill in FSP UPDs */
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parse_devicetree(params);
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/* Load VBT before devicetree-specific config. */
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params->GraphicsConfigPtr = (uintptr_t)vbt_get();
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/* Check if IGD is present and fill Graphics init param accordingly */
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
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params->PeiGraphicsPeimInit = 1;
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else
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params->PeiGraphicsPeimInit = 0;
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/* Use coreboot MP PPI services if Kconfig is enabled */
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if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
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params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
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params->SkipMpInit = 0;
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} else {
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params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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}
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/* Unlock upper 8 bytes of RTC RAM */
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params->RtcMemoryLock = 0;
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/* Legacy 8254 timer support */
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params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
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params->Enable8254ClockGatingOnS3 = 1;
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/* disable Legacy PME */
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memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
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/* USB configuration */
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for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
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params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
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params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
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params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
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params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
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params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
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params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
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}
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for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
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params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
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params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
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if (config->usb3_ports[i].tx_de_emp) {
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params->Usb3HsioTxDeEmphEnable[i] = 1;
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params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
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}
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if (config->usb3_ports[i].tx_downscale_amp) {
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params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
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params->Usb3HsioTxDownscaleAmp[i] =
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config->usb3_ports[i].tx_downscale_amp;
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}
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}
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/* SDCard related configuration */
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params->ScsSdCardEnabled = pcidev_path_on_root(PCH_DEVFN_SDCARD) ? dev->enabled : 0;
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params->Device4Enable = config->Device4Enable;
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/* eMMC configuration */
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dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
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if (!dev) {
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params->ScsEmmcEnabled = 0;
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} else {
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params->ScsEmmcEnabled = dev->enabled;
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params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
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}
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
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if (!dev || !xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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/* Provide correct UART number for FSP debug logs */
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params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
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/* Override/Fill FSP Silicon Param for mainboard */
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mainboard_silicon_init_params(params);
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}
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/* Mainboard GPIO Configuration */
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__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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/* Return list of SOC LPSS controllers */
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@ -86,6 +86,11 @@
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#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2)
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#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3)
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#if CONFIG(SOC_INTEL_JASPERLAKE)
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#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5)
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#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5)
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#endif
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#define PCH_DEV_SLOT_SIO3 0x15
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#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0)
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#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1)
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@ -122,6 +127,12 @@
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#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1)
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#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2)
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#if CONFIG(SOC_INTEL_JASPERLAKE)
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#define PCH_DEV_SLOT_STORAGE 0x1a
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#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0)
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#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0)
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#endif
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#define PCH_DEV_SLOT_PCIE 0x1c
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#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0)
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#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1)
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corp.
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* Copyright (C) 2019-2020 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -13,10 +13,113 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_tigerlake_config *config)
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{
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unsigned int i;
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const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
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uint32_t mask = 0;
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if (!dev || !dev->enabled) {
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/* Skip IGD initialization in FSP if device is disabled in devicetree.cb */
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m_cfg->InternalGfx = 0;
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m_cfg->IgdDvmt50PreAlloc = 0;
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} else {
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m_cfg->InternalGfx = 1;
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/* Set IGD stolen size to 60MB. */
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m_cfg->IgdDvmt50PreAlloc = 0xFE;
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}
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m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
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m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
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m_cfg->SaGv = config->SaGv;
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m_cfg->RMT = config->RMT;
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/* PCIe root port configuration */
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for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
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if (config->PcieRpEnable[i])
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mask |= (1 << i);
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}
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m_cfg->PcieRpEnableMask = mask;
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_Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcUsage) >=
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ARRAY_SIZE(config->PcieClkSrcUsage), "copy buffer overflow!");
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memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
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sizeof(config->PcieClkSrcUsage));
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_Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcClkReq) >=
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ARRAY_SIZE(config->PcieClkSrcClkReq), "copy buffer overflow!");
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memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
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sizeof(config->PcieClkSrcClkReq));
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m_cfg->PrmrrSize = config->PrmrrSize;
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m_cfg->EnableC6Dram = config->enable_c6dram;
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/* Disable BIOS Guard */
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m_cfg->BiosGuard = 0;
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/* Set CPU Ratio */
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m_cfg->CpuRatio = 0;
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m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
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DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB;
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/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
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m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
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/* Enable SMBus controller based on config */
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m_cfg->SmbusEnable = config->SmbusEnable;
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/* Set debug probe type */
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m_cfg->PlatformDebugConsent = config->DebugConsent;
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/* VT-d config */
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m_cfg->VtdDisable = 0;
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m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
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/* Audio */
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m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0;
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m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
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m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
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_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkDmicEnable) >=
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ARRAY_SIZE(config->PchHdaAudioLinkDmicEnable), "copy buffer overflow!");
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memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
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sizeof(config->PchHdaAudioLinkDmicEnable));
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_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSspEnable) >=
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ARRAY_SIZE(config->PchHdaAudioLinkSspEnable), "copy buffer overflow!");
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memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
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sizeof(config->PchHdaAudioLinkSspEnable));
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_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSndwEnable) >=
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ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!");
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memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
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sizeof(config->PchHdaAudioLinkSndwEnable));
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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/* TODO: Update with UPD override as FSP matures */
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const struct soc_intel_tigerlake_config *config = config_of_soc();
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FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
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soc_memory_init_params(m_cfg, config);
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mainboard_memory_init_params(mupd);
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}
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__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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@ -23,15 +23,6 @@
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#include <soc/soc_chip.h>
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#include <string.h>
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/* Debug interface flag */
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enum debug_interface_flag {
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DEBUG_INTERFACE_RAM = 0x1,
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DEBUG_INTERFACE_UART = 0x2,
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DEBUG_INTERFACE_USB3 = 0x4,
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DEBUG_INTERFACE_SERIAL_IO = 0x8,
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DEBUG_INTERFACE_TRACEHUB = 0x10
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};
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_tigerlake_config *config)
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{
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