mb/intel/adlrvp_n: Update devicetree
Update devicetree according to schematics. TEST=Build and boot Alder Lake N RVP. Change-Id: I9faee1cb3539a0246fc6a87e15b3150533de1ee5 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Krishna Prasad Bhat
Felix Held
parent
a6d642fa8d
commit
dbbb391700
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@ -16,20 +16,19 @@ chip soc/intel/alderlake
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# Sagv Configuration
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register "SaGv" = "SaGv_Enabled"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
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register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3
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register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2
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register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
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register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
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register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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@ -38,41 +37,20 @@ chip soc/intel/alderlake
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# Enable PCH PCIE RP 5 using CLK 2
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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# Enable PCH PCIE RP 7 using CLK 3
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 6 using CLK 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 8 using free running CLK (0x80)
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# Clock source is shared with LAN and hence marked as free running.
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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# Enable PCH PCIE RP 9 using CLK 1
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# Enable PCH PCIE RP 9 using CLK 0
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.clk_src = 0,
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.clk_req = 0,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 11 for optane
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register "pch_pcie_rp[PCH_RP(11)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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# Hybrid storage mode
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register "HybridStorageMode" = "1"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{
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@ -97,10 +75,10 @@ chip soc/intel/alderlake
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}"
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# TCSS USB3
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register "TcssAuxOri" = "0"
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register "TcssAuxOri" = "4"
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register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}"
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register "s0ix_enable" = "1"
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register "dptf_enable" = "1"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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@ -166,103 +144,7 @@ chip soc/intel/alderlake
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}"
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device domain 0 on
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device ref pcie5 on end
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device ref igpu on end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""Ambient""
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register "options.tsr[1].desc" = ""Battery""
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register "options.tsr[2].desc" = ""DDR""
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register "options.tsr[3].desc" = ""Skin""
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## Active Policy
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# TODO: below values are initial reference values only
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(95, 90),
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TEMP_PCT(90, 80),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {
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TEMP_PCT(80, 90),
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TEMP_PCT(70, 80),
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}
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}
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}"
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## Passive Policy
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# TODO: below values are initial reference values only
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000),
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[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000),
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}"
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## Critical Policy
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# TODO: below values are initial reference values only
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
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[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
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}"
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## Power Limits Control
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 35000,
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.max_power = 45000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 56000,
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.max_power = 56000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 3000 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref ipu on
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chip drivers/intel/mipi_camera
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register "acpi_uid" = "0x50000"
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@ -278,16 +160,8 @@ chip soc/intel/alderlake
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device generic 0 on end
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end
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end
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device ref pcie4_0 on end
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device ref pcie4_1 on end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tbt_pcie_rp2 on end
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device ref tbt_pcie_rp3 on end
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device ref crashlog off end
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device ref tcss_xhci on end
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device ref tcss_dma0 on end
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device ref tcss_dma1 on end
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device ref xhci on
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chip drivers/usb/acpi
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register "desc" = ""Root Hub""
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@ -397,14 +271,8 @@ chip soc/intel/alderlake
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device i2c 36 on end
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end
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end
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device ref pcie_rp1 on end
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device ref pcie_rp3 on end # W/A to FSP issue
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device ref pcie_rp4 on end # W/A to FSP issue
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device ref pcie_rp5 on end
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device ref pcie_rp6 on end
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device ref pcie_rp8 on end
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device ref pcie_rp7 on end
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device ref pcie_rp9 on end
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device ref pcie_rp11 on end
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device ref uart0 on end
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device ref gspi0 on end
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device ref p2sb on end
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@ -5,7 +5,6 @@ chip soc/intel/alderlake
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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use conn2 as mux_conn[2]
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device pnp 0c09.0 on end
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end
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end
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@ -21,10 +20,6 @@ chip soc/intel/alderlake
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register "desc" = ""TypeC Port 2""
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device ref tcss_usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""TypeC Port 3""
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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@ -36,24 +31,13 @@ chip soc/intel/alderlake
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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# SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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# SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 1 alias conn1 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port3 as usb2_port
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use tcss_usb3_port3 as usb3_port
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# SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 2 alias conn2 on end
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end
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end
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end
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end
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