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armv7: clean+invalidate all cache levels when disabling MMU 

This iterates thru all cache levels and cleans + invalidates all
data and unified caches before disabling dcache and MMU.

Change-Id: I8a671b4c90d7b88b8d0a95947bfa17f912cebaa2
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2930
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
David Hendricks 2013-03-26 21:39:03 -07:00
parent 19f3092b52
commit dbc11e2f76
1 changed files with 30 additions and 3 deletions
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33
src/arch/armv7/lib/cache.c
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@ -209,13 +209,40 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
dcache_op_mva(addr, len, OP_DCCIMVAC); dcache_op_mva(addr, len, OP_DCCIMVAC);
} }
void dcache_mmu_disable(void) void dcache_mmu_disable(void)
{ {
uint32_t sctlr; uint32_t sctlr, clidr;
int level;
clidr = read_clidr();
for (level = 0; level < 7; level++) {
unsigned int ctype = (clidr >> (level * 3)) & 0x7;
uint32_t csselr;
switch(ctype) {
case 0x0:
/* no cache */
break;
case 0x2:
case 0x4:
/* dcache only or unified cache */
csselr = level << 1;
write_csselr(csselr);
dcache_clean_invalidate_all();
break;
case 0x3:
/* separate icache and dcache */
csselr = level << 1;
write_csselr(csselr);
dcache_clean_invalidate_all();
break;
default:
/* reserved */
break;
}
}
sctlr = read_sctlr(); sctlr = read_sctlr();
dcache_clean_invalidate_all();
sctlr &= ~(SCTLR_C | SCTLR_M); sctlr &= ~(SCTLR_C | SCTLR_M);
write_sctlr(sctlr); write_sctlr(sctlr);
} }