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mb/google/kahlee/nuwani: Create Nuwani variant 

This commit creates a nuwani variant for Grunt. The initial settings
override the baseboard was copied from variant treeya.

BUG=b:144890301
TEST=emerge-grunt coreboot

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39316
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peichao Wang 2020-03-05 17:02:58 +08:00 committed by Martin Roth
parent 75985f1d0c
commit dbc958495d
14 changed files with 543 additions and 0 deletions
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1
src/mainboard/google/kahlee/Kconfig
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@ -66,6 +66,7 @@ config VARIANT_DIR
default "careena" if BOARD_GOOGLE_CAREENA
default "grunt" if BOARD_GOOGLE_GRUNT
default "liara" if BOARD_GOOGLE_LIARA
default "nuwani" if BOARD_GOOGLE_NUWANI
default "treeya" if BOARD_GOOGLE_TREEYA
config MAINBOARD_PART_NUMBER

3
src/mainboard/google/kahlee/Kconfig.name
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@ -12,6 +12,9 @@ config BOARD_GOOGLE_GRUNT
config BOARD_GOOGLE_LIARA
bool "-> Liara"
select BOARD_GOOGLE_BASEBOARD_KAHLEE
config BOARD_GOOGLE_NUWANI
bool "-> Nuwani"
select BOARD_GOOGLE_BASEBOARD_KAHLEE
config BOARD_GOOGLE_TREEYA
bool "-> Treeya"
select BOARD_GOOGLE_BASEBOARD_KAHLEE

20
src/mainboard/google/kahlee/variants/nuwani/Makefile.inc Normal file
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@ -0,0 +1,20 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2020 Google, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
subdirs-y += ./spd
romstage-y += ../baseboard/romstage.c
ramstage-y += mainboard.c

196
src/mainboard/google/kahlee/variants/nuwani/devicetree.cb Normal file
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@ -0,0 +1,196 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip soc/amd/stoneyridge
register "spd_addr_lookup" = "
{
{ {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
}"
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "16 * MiB"
register "stapm_percent" = "80"
register "stapm_time_ms" = "2000000"
register "stapm_power_mw" = "7800"
register "lvds_poseq_varybl_to_blon" = "0x5"
register "lvds_poseq_blon_to_varybl" = "0x5"
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 95,
.fall_time_ns = 3,
}"
# Enable I2C1 for H1 at 400kHz
register "i2c[1]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 3,
.fall_time_ns = 2,
}"
# Enable I2C2 for trackpad, pen at 400kHz
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 3,
.fall_time_ns = 2,
.data_hold_time_ns = 400,
}"
# Enable I2C3 for touchscreen at 400kHz
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 16,
.fall_time_ns = 8,
}"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on
device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU (Disabled for performance and battery)
device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
device pci 2.1 on end #
device pci 2.2 on end #
device pci 2.3 on end #
device pci 2.4 on
chip drivers/generic/bayhub
register "power_saving" = "1"
device pci 00.0 on end
end
end #
device pci 2.5 on end #
device pci 8.0 on end # PSP
device pci 9.0 on end # PCIe Host Bridge
device pci 9.2 on end # HDA
device pci 10.0 on end # xHCI
device pci 11.0 off end # SATA
device pci 12.0 on end # EHCI
device pci 14.0 on # SMbus
end # SMbus
device pci 14.3 on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC
device pci 14.7 on end # SD
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
end #domain
device mmio 0xfedc2000 on
chip drivers/generic/adau7002
device generic 0.0 on end
end
chip drivers/i2c/da7219
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)"
register "btn_cfg" = "50"
register "mic_det_thr" = "500"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
register "mclk_name" = ""oscout1""
device i2c 1a on end
end
chip drivers/generic/max98357a
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)"
register "sdmode_delay" = "5"
device generic 0.1 on end
end
end
device mmio 0xfedc3000 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "desc" = ""Cr50 TPM""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
device i2c 50 on end
end
end
device mmio 0xfedc4000 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)"
register "wake" = "7"
register "probed" = "1"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)"
register "generic.wake" = "7"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 0x2c on end
end
end
device mmio 0xfedc5000 on
chip drivers/i2c/hid
register "generic.hid" = ""SYTS7817""
register "generic.desc" = ""Synaptics Touchscreen""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)"
register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
register "generic.reset_delay_ms" = "45"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 20 on end
end
chip drivers/i2c/generic
register "hid" = ""RAYD0001""
register "desc" = ""Raydium Touchscreen""
register "probed" = "1"
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "1"
device i2c 39 on end
end
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "probed" = "1"
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "1"
device i2c 10 on end
end
end
end #chip soc/amd/stoneyridge

16
src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl Normal file
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@ -0,0 +1,16 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/gpe.asl>

17
src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl Normal file
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@ -0,0 +1,17 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/mainboard.asl>
#include <baseboard/acpi/audio.asl>

16
src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl Normal file
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@ -0,0 +1,16 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/routing.asl>

16
src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl Normal file
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@ -0,0 +1,16 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/sleep.asl>

16
src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl Normal file
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@ -0,0 +1,16 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/thermal.asl>

25
src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h Normal file
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@ -0,0 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/ec.h>
/* Enable Tablet switch */
#define EC_ENABLE_TBMC_DEVICE
/*
* Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in
* variant/gpio.h
*/
#define EC_ENABLE_SYNC_IRQ_GPIO

19
src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h Normal file
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@ -0,0 +1,19 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/gpio.h>
/* EC sync irq is AGPIO 10 */
#define EC_SYNC_IRQ 10

38
src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h Normal file
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@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef THERMAL_H
#define THERMAL_H
/*
* Stoney Ridge Thermal Requirements 12 (6W)
* TDP (W) 6
* T die,max (°C) 95
* T ctl,max 85
* T die,lmt (default) 90
* T ctl,lmt (default) 80
*/
/* Control TDP Settings */
#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 94
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 85
#endif

126
src/mainboard/google/kahlee/variants/nuwani/mainboard.c Normal file
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@ -0,0 +1,126 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <ec/google/chromeec/ec.h>
#include <baseboard/variants.h>
#include <boardid.h>
#include <cbfs.h>
#include <gpio.h>
#include <smbios.h>
#include <variant/gpio.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <drivers/generic/bayhub/bh720.h>
uint32_t sku_id(void)
{
static int sku = -1;
if (sku == -1)
sku = google_chromeec_get_sku_id();
return sku;
}
uint8_t variant_board_sku(void)
{
return sku_id();
}
void variant_mainboard_suspend_resume(void)
{
/* Enable backlight - GPIO 133 active low */
gpio_set(GPIO_133, 0);
}
void board_bh720(struct device *dev)
{
u32 sdbar;
u32 bh720_pcr_data;
sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
/* Enable Memory Access Function */
write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000);
write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
/* Set EMMC VCCQ 1.8V PCR 0x308[4] */
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING);
bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
write32((void *)(sdbar + BH720_MEM_RW_DATA),
bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V);
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
/* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL);
bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
bh720_pcr_data &= 0x0000FFFF;
bh720_pcr_data |= 0x2510 << 16;
write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data);
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL);
/* Use PLL Base clock PCR 0x3E4[22] = 1 */
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_READ | BH720_PCR_CSR);
bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
write32((void *)(sdbar + BH720_MEM_RW_DATA),
bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL);
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_WRITE | BH720_PCR_CSR);
/* Disable Memory Access */
write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
/* Tune VIH */
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
bh720_pcr_data &= 0xFFFFFF00;
/* CLK = 3 and DAT = 2 */
bh720_pcr_data |= 0x35;
pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
}
const char *smbios_mainboard_manufacturer(void)
{
static char oem_bin_data[11];
static const char *manuf;
if (!CONFIG(USE_OEM_BIN))
return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
if (manuf)
return manuf;
if (cbfs_boot_load_file("oem.bin", oem_bin_data,
sizeof(oem_bin_data) - 1,
CBFS_TYPE_RAW))
manuf = &oem_bin_data[0];
else
manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
return manuf;
}

34
src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc Normal file
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@ -0,0 +1,34 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
## Copyright (C) 2015 Intel Corporation.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000
SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001
SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010
SPD_SOURCES += micron-MT40A1G16KNR-075-E # 0b0011
SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0100
SPD_SOURCES += samsung-K4AAG165WB-MCRC # 0b0101
SPD_SOURCES += micron-MT40A512M16LY-075-E # 0b0110
SPD_SOURCES += hynix-H5ANAG6NCMR-VKC # 0b0111
SPD_SOURCES += hynix-H5AN8G6NCJR-VKC # 0b1000
SPD_SOURCES += samsung-K4A8G165WC-BCTD # 0b1001
SPD_SOURCES += samsung-K4AAG165WB-MCTD # 0b1010
SPD_SOURCES += micron-MT40A512M16TB-062E-J # 0b1011
SPD_SOURCES += samsung-K4A8G165WC-BCWE # 0b1100
SPD_SOURCES += hynix-H5AN8G6NCJR-XNC # 0b1101
SPD_SOURCES += empty # 0b1110
SPD_SOURCES += empty # 0b1111