GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge: Remove DEV_D18F4 definition 

The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is
the same as SOC_PM_DEV. Remove the definition, and replace its use in
tsc_freq.c with SOC_PM_DEV.

BUG=b:117754424
TEST=Build and boot grunt.

Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Richard Spiegel 2018-10-17 09:54:12 -07:00 committed by Patrick Georgi
parent 63405dacb7
commit dbd9ea070e
2 changed files with 1 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/amd/stoneyridge/include/soc/pci_devs.h
View File

@ -145,12 +145,6 @@
#define PM_DEVID 0x15b4
#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)
#define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC)
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#define DEV_D18F4 dev_find_slot(0, PM_DEVFN)
#else
#define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC)
#endif
/* Northbridge Configuration */
#define NB_DEV 0x18

2
src/soc/amd/stoneyridge/tsc_freq.c
View File

@ -36,7 +36,7 @@ unsigned long tsc_freq_mhz(void)
* to the "Software P-state Numbering" section, P0 is the highest
* non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
*/
boost_states = (pci_read_config32(DEV_D18F4, CORE_PERF_BOOST_CTRL)
boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL)
>> 2) & 0x7;
msr = rdmsr(PSTATE_0_MSR + boost_states);