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- Bump the LinuxBIOS major version 

- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2004-10-21 10:44:08 +00:00
parent f3aa4707d3
commit dbec2d4090
107 changed files with 1368 additions and 1540 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
NEWS
View File

@ -1,3 +1,10 @@
- 1.1.7
- The configuration language has been cleaned up. No more link keyword.
- Everything is now in the device tree.
- The static and dynamic device trees have been unified
- Support for setting the pci subsystem vendor and pci subsystem device has been added.
- 64bit resource support
- Generic smbus support
- 1.1.6
- pnp/superio devices are now handled cleanly with very little code
- Initial support for finding x86 BIST errors

2
src/config/Options.lb
View File

@ -122,7 +122,7 @@ define OBJCOPY
comment "Objcopy command"
end
define LINUXBIOS_VERSION
default "1.1.6"
default "1.1.7"
export always
format "\"%s\""
comment "LinuxBIOS version"

2
src/cpu/intel/slot_2/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control cpu_intel_slot_2_control;
extern struct chip_operations cpu_intel_slot_2_control;
struct cpu_intel_slot_2_config {
};

2
src/cpu/intel/slot_2/slot_2.c
View File

@ -2,6 +2,6 @@
#include "chip.h"
struct chip_control cpu_intel_slot_2_control = {
struct chip_operations cpu_intel_slot_2_control = {
.name = "slot 2",
};

2
src/cpu/intel/socket_mPGA603/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control cpu_intel_socket_mPGA603_400Mhz_control;
extern struct chip_operations cpu_intel_socket_mPGA603_400Mhz_control;
struct cpu_intel_socket_mPGA603_400Mhz_config {
};

2
src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c
View File

@ -2,6 +2,6 @@
#include "chip.h"
struct chip_control cpu_intel_socket_mPGA603_400Mhz_control = {
struct chip_opertations cpu_intel_socket_mPGA603_400Mhz_control = {
.name = "socket mPGA603_400Mhz",
};

2
src/cpu/intel/socket_mPGA604_533Mhz/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control cpu_intel_socket_mPGA604_533Mhz_control;
extern struct chip_operations cpu_intel_socket_mPGA604_533Mhz_control;
struct cpu_intel_socket_mPGA604_533Mhz_config {
};

2
src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c
View File

@ -2,6 +2,6 @@
#include "chip.h"
struct chip_control cpu_intel_socket_mPGA604_533Mhz_control = {
struct chip_operations cpu_intel_socket_mPGA604_533Mhz_control = {
.name = "socket mPGA604_533Mhz",
};

2
src/cpu/intel/socket_mPGA604_800Mhz/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control cpu_intel_socket_mPGA604_800Mhz_control;
extern struct chip_operations cpu_intel_socket_mPGA604_800Mhz_control;
struct cpu_intel_socket_mPGA604_800Mhz_config {
};

2
src/cpu/intel/socket_mPGA604_800Mhz/socket_mPGA604_800Mhz.c
View File

@ -2,6 +2,6 @@
#include "chip.h"
struct chip_control cpu_intel_socket_mPGA604_800Mhz_control = {
struct chip_operations cpu_intel_socket_mPGA604_800Mhz_control = {
.name = "socket mPGA604_800Mhz",
};

17
src/devices/device.c
View File

@ -320,15 +320,6 @@ void compute_allocate_resource(
bridge->align = resource->align;
}
/* Propogate the resource limit to the bridge register */
if (bridge->limit > resource->limit) {
bridge->limit = resource->limit;
}
/* Artificially deny limits between DEVICE_MEM_HIGH and 0xffffffff */
if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit <= 0xffffffff)) {
bridge->limit = DEVICE_MEM_HIGH;
}
/* Make certain we are dealing with a good minimum size */
size = resource->size;
align = resource->align;
@ -338,6 +329,14 @@ void compute_allocate_resource(
if (resource->flags & IORESOURCE_FIXED) {
continue;
}
/* Propogate the resource limit to the bridge register */
if (bridge->limit > resource->limit) {
bridge->limit = resource->limit;
}
/* Artificially deny limits between DEVICE_MEM_HIGH and 0xffffffff */
if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit <= 0xffffffff)) {
bridge->limit = DEVICE_MEM_HIGH;
}
if (resource->flags & IORESOURCE_IO) {
/* Don't allow potential aliases over the
* legacy pci expansion card addresses.

8
src/devices/pci_device.c
View File

@ -485,7 +485,7 @@ void pci_dev_enable_resources(struct device *dev)
/* Set the subsystem vendor and device id for mainboard devices */
ops = ops_pci(dev);
if (dev->chip_ops && ops && ops->set_subsystem) {
if (dev->on_mainboard && ops && ops->set_subsystem) {
printk_debug("%s subsystem <- %02x/%02x\n",
dev_path(dev),
MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
@ -499,8 +499,6 @@ void pci_dev_enable_resources(struct device *dev)
command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
enable_childrens_resources(dev);
}
void pci_bus_enable_resources(struct device *dev)
@ -513,9 +511,11 @@ void pci_bus_enable_resources(struct device *dev)
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));

31
src/devices/pnp_device.c
View File

@ -132,7 +132,7 @@ struct device_operations pnp_ops = {
static void pnp_get_ioresource(device_t dev, unsigned index, struct io_info *info)
{
struct resource *resource;
uint32_t size;
unsigned moving, gran, step;
resource = new_resource(dev, index);
@ -140,11 +140,32 @@ static void pnp_get_ioresource(device_t dev, unsigned index, struct io_info *inf
resource->limit = 0xffff;
resource->flags |= IORESOURCE_IO;
/* Get the resource size */
moving = info->mask;
gran = 15;
step = 1 << gran;
/* Find the first bit that moves */
while((moving & step) == 0) {
gran--;
step >>= 1;
}
/* Now find the first bit that does not move */
while((moving & step) != 0) {
gran--;
step >>= 1;
}
/* Of the moving bits the last bit in the first group,
* tells us the size of this resource.
*/
if ((moving & step) == 0) {
gran++;
step <<= 1;
}
/* Set the resource size and alignment */
size = (0xffff & info->mask);
resource->size = (~(size | 0xfffff800) + 1);
resource->align = log2(resource->size);
resource->gran = resource->align;
resource->gran = gran;
resource->align = gran;
resource->limit = info->mask | (step - 1);
resource->size = 1 << gran;
}
static void get_resources(device_t dev, struct pnp_info *info)

9
src/devices/root_device.c
View File

@ -151,11 +151,10 @@ void root_dev_init(device_t root)
* @brief Default device operation for root device
*
* This is the default device operation for root devices in PCI based systems.
* The static enumeration code chip_control::enumerate() of mainboards usually
* override this operation with their own device operations. An notable
* example is mainboard operations for AMD K8 mainboards. They replace the
* scan_bus() method with amdk8_scan_root_bus() due to the special device
* layout of AMD K8 systems.
* These operations should be fully usable as is. However the
* chip_operations::dev_enable of a motherboard can override this if you
* want non-default behavior. Currently src/mainboard/arima/hdama/mainbaord.c
* does this for debugging purposes.
*/
struct device_operations default_dev_ops_root = {
.read_resources = root_dev_read_resources,

1
src/include/device/device.h
View File

@ -59,6 +59,7 @@ struct device {
unsigned int enabled : 1; /* set if we should enable the device */
unsigned int initialized : 1; /* set if we have initialized the device */
unsigned int have_resources : 1; /* Set if we have read the devices resources */
unsigned int on_mainboard : 1;
uint8_t command;

1
src/include/device/pci.h
View File

@ -50,6 +50,7 @@ void pci_bus_enable_resources(device_t dev);
unsigned int pci_scan_bridge(device_t bus, unsigned int max);
unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max);
struct resource *pci_get_resource(struct device *dev, unsigned long index);
void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device);
#define PCI_IO_BRIDGE_ALIGN 4096
#define PCI_MEM_BRIDGE_ALIGN (1024*1024)

6
src/include/pc80/isa-dma.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef PC80_ISA_DMA_H
#define PC80_ISA_DMA_H
void isa_dma_init(void);
#endif /* PC80_ISA_DMA_H */

133
src/mainboard/Iwill/DK8S2/Config.lb
View File

@ -242,95 +242,92 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on # LDT 0
chip southbridge/amd/amd8131
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b on # HW Monitor
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}"
# register "lpt" = "{1}"
end
# superio winbond/w83627hf link 1
# pnp 2e.0
# pnp 2e.1
# pnp 2e.2
# pnp 2e.3
# pnp 2e.4
# pnp 2e.5
# pnp 2e.6
# pnp 2e.7
# pnp 2e.8
# pnp 2e.9
# pnp 2e.a
# register "com1" = "{1, 0, 0x3f8, 4}"
# register "lpt" = "{1}"
# end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
end # LDT0
device pci 18.0 on end # LDT1
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt0" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
##

2
src/mainboard/Iwill/DK8S2/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_Iwill_DK8S2_control;
extern struct chip_operations mainboard_Iwill_DK8S2_control;
struct mainboard_Iwill_DK8S2_config {
int nothing;

26
src/mainboard/Iwill/DK8S2/mainboard.c
View File

@ -9,31 +9,7 @@
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_Iwill_DK8S2_control = {
struct chip_operations mainboard_Iwill_DK8S2_control = {
.enumerate = enumerate,
.name = "Iwill DK8S2 mainboard ",
};

114
src/mainboard/Iwill/DK8X/Config.lb
View File

@ -239,63 +239,71 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627thf link 1
pnp 2e.0
pnp 2e.1
pnp 2e.2
pnp 2e.3
pnp 2e.4
pnp 2e.5
pnp 2e.6
pnp 2e.7
pnp 2e.8
pnp 2e.9
pnp 2e.a
register "com1" = "{1, 0, 0x3f8, 4}"
register "lpt" = "{1}"
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/winbond/w83627thf
device pnp 2e.0 on end
device pnp 2e.1 on end
device pnp 2e.2 on end
device pnp 2e.3 on end
device pnp 2e.4 on end
device pnp 2e.5 on end
device pnp 2e.6 on end
device pnp 2e.7 on end
device pnp 2e.8 on end
device pnp 2e.9 on end
device pnp 2e.a on end
end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
end # LDT0
device pci 18.0 on end # LDT1
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt0" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
##

2
src/mainboard/Iwill/DK8X/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_arima_hdama_control;
extern struct chip_operations mainboard_arima_hdama_control;
struct mainboard_arima_hdama_config {
int nothing;

28
src/mainboard/Iwill/DK8X/mainboard.c
View File

@ -8,33 +8,7 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_arima_hdama_control = {
.enumerate = enumerate,
struct chip_operations mainboard_arima_hdama_control = {
.name = "Arima HDAMA mainboard ",
};

167
src/mainboard/amd/quartet/Config.lb
View File

@ -251,102 +251,115 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8111 "amd8111" link 2
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 on
pci 0:1.6 on
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 on
superio NSC/pc87360 link 1
pnp 2e.0 off # Floppy
chip northbridge/amd/amdk8 # mc0
device pci_domain 0 on
device pci 18.0 on end
device pci 18.0 on end
device pci 18.0
chip southbridge amd/amd8111
device pci 0:0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 on end
end
device pci 1.0 on
chip superio/NSC/pc87360
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
end
device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
end
device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
end
device pnp 2e.7 off end # GPIO
device pnp 2e.8 off end # ACB
device pnp 2e.9 off end # FSCM
device pnp 2e.a off end # WDT
end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
southbridge amd/amd8131 "amd8131_0" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 on end
device pci 1.6 on end
end
southbridge amd/amd8131 "amd8131_1" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
northbridge amd/amdk8 "mc2"
pci 0:1a.0
pci 0:1a.0
pci 0:1a.0
pci 0:1a.1
pci 0:1a.2
pci 0:1a.3
end
chip northbridge/amd/amdk8 # mc1
device pci 19.0 on end
device pci 19.0 on
chip southbridge amd/amd8131 # amd8131_0
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge amd/amd8131 # amd8131_1
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
northbridge amd/amdk8 "mc3"
pci 0:1b.0
pci 0:1b.0
pci 0:1b.0
pci 0:1b.1
pci 0:1b.2
pci 0:1b.3
end
chip northbridge/amd/amdk8 # mc2
device pci 1a.0 on end
device pci 1a.0 on end
device pci 1a.0 on end
device pci 1a.1 on end
device pci 1a.2 on end
device pci 1a.3 on end
end
cpu k8 "cpu0"
end
cpu k8 "cpu1"
end
cpu k8 "cpu2"
end
cpu k8 "cpu3"
chip northbridge/amd/amdk8 # mc3
device pci 1b.0 on end
device pci 1b.0 on end
device pci 1b.0 on end
device pci 1b.1 on end
device pci 1b.2 on end
device pci 1b.3 on end
end
end # pci_domain 0
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
chip cpu/amd/socket_940
device apic 2 on end
end
chip cpu/amd/socket_940
device apic 3 on end
end
end
end
##

2
src/mainboard/amd/quartet/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_amd_quartet_control;
extern struct chip_operations mainboard_amd_quartet_control;
struct mainboard_amd_quartet_config {
int nothing;

32
src/mainboard/amd/quartet/mainboard.c
View File

@ -8,37 +8,7 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1, 2, 3,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
if (chip->control && chip->control->name) {
printk_debug("Enumerating: %s\n", chip->control->name);
}
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_amd_quartet_control = {
.enumerate = enumerate,
struct chip_operations mainboard_amd_quartet_control = {
.name = "AMD Quartet mainboard ",
};

117
src/mainboard/amd/serenade/Config.lb
View File

@ -251,76 +251,91 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 2
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
chip northbridage/amd/amdk8 # mc0
device pci_domain 0 on
device pci 18.0 on end # LDT 0
device pci 18.0 on end # LDT1
device pci 18.0 on # LDT2
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
southbridge amd/amd8111 "amd8111" link 2
#pci 0:0.0
#pci 0:1.0 on
#pci 0:1.1 on
#pci 0:1.2 on
#pci 0:1.3 on
#pci 0:1.5 off
#pci 0:1.6 off
#pci 1:0.0 on
#pci 1:0.1 on
#pci 1:0.2 on
#pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/windond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
end
device pnp 2e.2 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
end
device pnp 2e.3 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b on # HW Monitor
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAM_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
end # device pci 18.0
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
cpu k8 "cpu0"
register "ldt2" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apci_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
##

2
src/mainboard/amd/serenade/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_amd_serenade_control;
extern struct chip_operations mainboard_amd_serenade_control;
struct mainboard_amd_serenade_config {
int nothing;

33
src/mainboard/amd/serenade/mainboard.c
View File

@ -8,37 +8,6 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
if (chip->control && chip->control->name) {
printk_debug("Enumerating: %s\n", chip->control->name);
}
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_amd_serenade_control = {
.enumerate = enumerate,
struct chip_operations mainboard_amd_serenade_control = {
.name = "AMD Serenade mainboard ",
};

2
src/mainboard/amd/solo/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_amd_solo_control;
extern struct chip_operations mainboard_amd_solo_control;
struct mainboard_amd_solo_config {
int nothing;

26
src/mainboard/amd/solo/mainboard.c
View File

@ -10,30 +10,6 @@
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] = {
0,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_amd_solo_control = {
.enumerate = enumerate,
struct chip_operations mainboard_amd_solo_control = {
.name = "AMD Solo7 mainboard ",
};

6
src/mainboard/arima/hdama/Config.lb
View File

@ -123,7 +123,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
dir /pc80
config chip.h
# sample config for arima/hdama
# config for arima/hdama
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on # northbridge
@ -141,7 +141,7 @@ chip northbridge/amd/amdk8
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 0.2 off end
device pci 1.0 off end
end
device pci 1.0 on
@ -218,6 +218,8 @@ chip northbridge/amd/amdk8
end
device pci 1.5 off end
device pci 1.6 on end
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
end # device pci 18.0

7
src/mainboard/arima/hdama/Options.lb
View File

@ -29,9 +29,11 @@ uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -117,6 +119,9 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="HDAMA"
default MAINBOARD_VENDOR="ARIMA"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
### LinuxBIOS layout values

2
src/mainboard/arima/hdama/mainboard.c
View File

@ -313,7 +313,7 @@ static struct device_operations mainboard_operations = {
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_arima_hdama_ops = {
.name = "Arima HDAMA mainboard ",

2
src/mainboard/densitron/dpx114/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_densitron_dpx114_control;
extern struct chip_operations mainboard_densitron_dpx114_control;
struct mainboard_densitron_dpx114_config {
int nothing;

18
src/mainboard/densitron/dpx114/mainboard.c
View File

@ -20,24 +20,18 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_via_epia_control = {
.enumerate = enumerate,
struct chip_operations mainboard_via_epia_control = {
.enable_dev = enable_dev,
.name = "VIA EPIA mainboard ",
};

2
src/mainboard/digitallogic/adl855pc/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_digitallogic_adl855pc_control;
extern struct chip_operations mainboard_digitallogic_adl855pc_control;
struct mainboard_digitallogic_adl855pc_config {
int nothing;

18
src/mainboard/digitallogic/adl855pc/mainboard.c
View File

@ -20,24 +20,18 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_digitallogic_adl855pc_control = {
.enumerate = enumerate,
struct chip_operations mainboard_digitallogic_adl855pc_control = {
.enable_dev = enable_dev,
.name = "Digital Logic ADL855PC mainboard ",
};

2
src/mainboard/emulation/qemu-i386/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_emulation_qemu_i386_control;
extern struct chip_operations mainboard_emulation_qemu_i386_control;
struct mainboard_emulation_qemu_i386_config {
int nothing;

24
src/mainboard/emulation/qemu-i386/mainboard.c
View File

@ -7,11 +7,6 @@
#include <arch/io.h>
#include "chip.h"
void cpufixup(unsigned long mem)
{
printk_spew("Welcome to LinuxBIOS CPU fixup. done.\n");
}
static int mainboard_scan_bus(device_t root, int maxbus)
{
int retval;
@ -24,25 +19,18 @@ static int mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(struct device *dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_emulation_qemu_i386_control = {
.enumerate = enumerate,
struct chip_operations mainboard_emulation_qemu_i386_control = {
.enable_dev = enable_dev,
.name = "qemu mainboard ",
};

114
src/mainboard/ibm/e325/Config.lb
View File

@ -251,73 +251,85 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on end # LDT 0
device pci 18.0 on # LDT 1
chip southbridge/amd/amd8131
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
southbridge amd/amd8111 "amd8111" link 1
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio NSC/pc87366 link 1
pnp 2e.0 off # Floppy
chip southbridge/amd/amd8111
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/NSC/pc87366
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
end
device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
end
device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
end
device pnp 2e.7 off end # GPIO
device pnp 2e.8 off end # ACB
device pnp 2e.9 off end # FSCM
device pnp 2e.a off end # WDT
end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
end # device pci 18.0
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt1" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
##

2
src/mainboard/ibm/e325/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_ibm_e325_control;
extern struct chip_operations mainboard_ibm_e325_control;
struct mainboard_ibm_e325_config {
int nothing;

34
src/mainboard/ibm/e325/mainboard.c
View File

@ -8,38 +8,6 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
if (chip->control && chip->control->name) {
printk_debug("Enumerating: %s\n", chip->control->name);
}
/* update device operation for dynamic root */
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_ibm_e325_control = {
.enumerate = enumerate,
struct chip_operations mainboard_ibm_e325_control = {
.name = "IBM E325 mainboard ",
};

114
src/mainboard/newisys/khepri/Config.lb
View File

@ -253,73 +253,85 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on end # LDT 0
device pci 18.0 on # LDT 1
chip southbridge/amd/amd8131
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
southbridge amd/amd8111 "amd8111" link 1
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 on
pci 0:1.6 on
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 on
superio NSC/pc87360 link 1
pnp 2e.0 off # Floppy
chip southbridge/amd/amd8111
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on end
device pci 1.0 on end
end
device pci 1.0 on
chip superio/NSC/pc87360
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 off # Com 2
end
device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.3 on # Com 1
end
device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.4 off # SWC
pnp 2e.5 off # Mouse
pnp 2e.6 on # Keyboard
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.7 off # GPIO
pnp 2e.8 off # ACB
pnp 2e.9 off # FSCM
pnp 2e.a off # WDT
end
device pnp 2e.7 off end # GPIO
device pnp 2e.8 off end # ACB
device pnp 2e.9 off end # FSCM
device pnp 2e.a off end # WDT
end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 on end
device pci 1.6 on end
end
end # LDT1
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "ldt1" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end
##

2
src/mainboard/newisys/khepri/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_newisys_khepri_control;
extern struct chip_operations mainboard_newisys_khepri_control;
struct mainboard_newisys_khepri_config {
int nothing;

28
src/mainboard/newisys/khepri/mainboard.c
View File

@ -8,33 +8,7 @@
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1,
};
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_newisys_khepri_control = {
.enumerate = enumerate,
struct chip_operations mainboard_newisys_khepri_control = {
.name = "Newisys Khepri mainboard ",
};

15
src/mainboard/technologic/ts5300/Config.lb
View File

@ -210,22 +210,13 @@ mainboardinit ./auto.inc
dir /pc80
config chip.h
northbridge amd/sc520 "elan_nb"
southbridge amd/sc520 "elan_sb"
chip northbridge/amd/sc520
chip southbridge amd/sc520
register "enable_usb" = "0"
register "enable_native_ide" = "1"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
end
chip cpu/amd/sc520
end
cpu p6 "cpu0"
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc

2
src/mainboard/technologic/ts5300/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_technologic_ts5300_control;
extern struct chip_operations mainboard_technologic_ts5300_control;
struct mainboard_technologic_ts5300_config {
int nothing;

20
src/mainboard/technologic/ts5300/mainboard.c
View File

@ -20,24 +20,18 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainbaord_operations;
}
struct chip_control mainboard_technologic_ts5300_control = {
.enumerate = enumerate,
struct chip_operations mainboard_technologic_ts5300_control = {
.enable_dev = enable_dev,
.name = "Technologic Systems TS5300 mainboard ",
};

106
src/mainboard/tyan/s2735/Config.lb
View File

@ -152,71 +152,79 @@ mainboardinit cpu/p6/disable_mmx_sse.inc
config chip.h
northbridge intel/e7501 "e7501"
pci 0:2.0
pci 0:0.0
pci 0:0.1
pci 0:6.0
southbridge intel/i82870 "i82870"
pci 0:1c.0
pci 0:1d.0
pci 0:1e.0
pci 0:1f.0
chip northbridge/intel/e7501
device pci_domain 0
device pci 0.0 on end
device pci 0.1 on end
device pci 2.0 on
chip southbridge/intel/i82870
device pci 1c.0
device pci 1d.0
device pci 1e.0
device pci 1f.0
end
end
southbridge intel/i82801er "i82801er"
pci 0:1f.0
pci 0:1d.0 on
pci 0:1d.1 on
pci 0:1d.2 on
pci 0:1d.3 on
pci 0:1d.7 on
pci 0:1e.0 on
pci 0:1f.1 off
pci 0:1f.2 on
pci 0:1f.3 on
pci 0:1f.5 off
pci 0:1f.6 off
# pci 1:8.0 off
superio winbond/w83627hf
pnp 2e.0 on # Floppy
end
device pci 6.0 on end
chip southbridge/intel/i82801er
device pci 1d.0 on end
device pci 1d.1 on end
device pci 1d.2 on end
device pci 1d.3 on end
device pci 1d.7 on end
device pci 1e.0 on end
device pci 1f.0 on
# device pci 8.0 end
chip winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b on # HW Monitor
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
#end
end
device pci 1f.1 off end
device pci 1f.2 on end
device pci 1f.3 on end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
device apic_cluster 0
chip cpu/intel/socket_mPGA604_533Mhz
apic 0
end
chip cpu/intel/socket_mPGA604_533Mhz
apic 6
end
end
end
dir /pc80
#dir /bioscall
cpu p6 "cpu0"
end
cpu p6 "cpu1"
end
cpu p6 "cpu2"
end
cpu p6 "cpu3"
end

2
src/mainboard/tyan/s2735/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_tyan_s2735_control;
extern struct chip_operations mainboard_tyan_s2735_control;
struct mainboard_tyan_s2735_config {
int fixup_scsi;

49
src/mainboard/tyan/s2735/mainboard.c
View File

@ -6,10 +6,7 @@
#include "chip.h"
//#include <part/mainboard.h>
//#include "lsi_scsi.c"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 6, 1, 7
};
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
@ -122,29 +119,6 @@ static void vga_fixup(void) {
}
*/
static void
enable(struct chip *chip, enum chip_pass pass)
{
struct mainboard_tyan_s2735_config *conf =
(struct mainboard_tyan_s2735_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_PRE_CONSOLE:
// case CONF_PASS_PRE_PCI:
case CONF_PASS_POST_PCI:
case CONF_PASS_PRE_BOOT:
// if (conf->fixup_scsi)
// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
// printk_debug("mainboard fixup pass %d done\r\n",pass);
break;
}
}
static int
mainboard_scan_bus(device_t root, int maxbus)
{
@ -158,25 +132,18 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_ops;
}
struct chip_control mainboard_tyan_s2735_control = {
.enable = enable,
.enumerate = enumerate,
struct chip_operations mainboard_tyan_s2735_control = {
.enable_dev = enable_dev,
.name = "Tyan s2735 mainboard ",
};

2
src/mainboard/via/epia-m/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_via_epia_m_control;
extern struct chip_operations mainboard_via_epia_m_control;
struct mainboard_via_epia_m_config {
int nothing;

43
src/mainboard/via/epia-m/mainboard.c
View File

@ -47,51 +47,22 @@ void write_protect_vgabios(void)
}
static void
enable(struct chip *chip, enum chip_pass pass)
{
struct mainboard_tyan_s4882_config *conf =
(struct mainboard_tyan_s4882_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_PRE_CONSOLE:
// case CONF_PASS_PRE_PCI:
case CONF_PASS_POST_PCI:
// case CONF_PASS_PRE_BOOT:
// if (conf->fixup_scsi)
// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
printk_debug("mainboard fixup pass %d done\r\n",
pass);
break;
}
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_via_epia_m_control = {
.enumerate = enumerate,
struct chip_operations mainboard_via_epia_m_control = {
.enable_dev = enable_dev,
.name = "VIA EPIA-M mainboard ",
.enable = enable
};

2
src/mainboard/via/epia/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_control mainboard_via_epia_control;
extern struct chip_operations mainboard_via_epia_control;
struct mainboard_via_epia_config {
int nothing;

19
src/mainboard/via/epia/mainboard.c
View File

@ -20,24 +20,19 @@ mainboard_scan_bus(device_t root, int maxbus)
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
static void enable_dev(device_t dev)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
dev->ops = &mainboard_operations;
}
struct chip_control mainboard_via_epia_control = {
.enumerate = enumerate,
struct chip_operations mainboard_via_epia_control = {
.enable_dev = enable_dev,
.name = "VIA EPIA mainboard ",
};

7
src/northbridge/amd/amdk8/northbridge.c
View File

@ -441,6 +441,11 @@ static void amdk8_set_resources(device_t dev)
}
}
static void amdk8_enable_resources(device_t dev)
{
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static void mcf0_control_init(struct device *dev)
{
@ -470,7 +475,7 @@ static void mcf0_control_init(struct device *dev)
static struct device_operations northbridge_operations = {
.read_resources = amdk8_read_resources,
.set_resources = amdk8_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable_resources = amdk8_enable_resources,
.init = mcf0_control_init,
.scan_bus = amdk8_scan_chains,
.enable = 0,

2
src/northbridge/emulation/qemu-i386/chip.h
View File

@ -2,4 +2,4 @@ struct northbridge_emulation_qemu_i386_config
{
};
extern struct chip_control northbridge_emulation_qemu_i386_control;
extern struct chip_operations northbridge_emulation_qemu_i386_control;

43
src/northbridge/emulation/qemu-i386/northbridge.c
View File

@ -68,47 +68,6 @@ struct mem_range *sizeram(void)
return mem;
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
static void random_fixup() {
device_t pcidev = dev_find_slot(0, 0);
printk_warning("QEMU random fixup ...\n");
if (pcidev) {
// pci_write_config8(pcidev, 0x0, 0x0);
}
}
static void northbridge_init(struct chip *chip, enum chip_pass pass)
{
struct northbridge_dummy_qemu_i386_config *conf =
(struct northbridge_dummy_qemu_i386_config *)chip->chip_info;
switch (pass) {
case CONF_PASS_PRE_PCI:
break;
case CONF_PASS_POST_PCI:
break;
case CONF_PASS_PRE_BOOT:
random_fixup();
break;
default:
/* nothing yet */
break;
}
}
struct chip_control northbridge_emulation_qemu_i386_control = {
.enumerate = enumerate,
.enable = northbridge_init,
struct chip_operations northbridge_emulation_qemu_i386_control = {
.name = "QEMU Northbridge",
};

2
src/northbridge/intel/855pm/chip.h
View File

@ -2,4 +2,4 @@ struct northbridge_intel_855pm_config
{
};
extern struct chip_control northbridge_intel_855pm_control;
extern struct chip_operations northbridge_intel_855pm_control;

35
src/northbridge/intel/855pm/northbridge.c
View File

@ -113,38 +113,7 @@ struct mem_range *sizeram(void)
return mem;
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
#if 0
static void northbridge_init(struct chip *chip, enum chip_pass pass)
{
struct northbridge_intel_855pm_config *conf =
(struct northbridge_intel_855pm_config *)chip->chip_info;
switch (pass) {
case CONF_PASS_PRE_PCI:
break;
case CONF_PASS_POST_PCI:
break;
case CONF_PASS_PRE_BOOT:
break;
default:
/* nothing yet */
break;
}
}
#endif
struct chip_control northbridge_intel_855pm_control = {
.enumerate = enumerate,
// .enable = northbridge_init,
.name = "intel E7501 Northbridge",
struct chip_operations northbridge_intel_855pm_control = {
.name = "intel 855pm Northbridge",
};

2
src/northbridge/intel/e7501/chip.h
View File

@ -2,4 +2,4 @@ struct northbridge_intel_e7501_config
{
};
extern struct chip_control northbridge_intel_e7501_control;
extern struct chip_operations northbridge_intel_e7501_control;

33
src/northbridge/intel/e7501/northbridge.c
View File

@ -113,38 +113,7 @@ struct mem_range *sizeram(void)
return mem;
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
#if 0
static void northbridge_init(struct chip *chip, enum chip_pass pass)
{
struct northbridge_intel_e7501_config *conf =
(struct northbridge_intel_e7501_config *)chip->chip_info;
switch (pass) {
case CONF_PASS_PRE_PCI:
break;
case CONF_PASS_POST_PCI:
break;
case CONF_PASS_PRE_BOOT:
break;
default:
/* nothing yet */
break;
}
}
#endif
struct chip_control northbridge_intel_e7501_control = {
.enumerate = enumerate,
// .enable = northbridge_init,
struct chip_operations northbridge_intel_e7501_control = {
.name = "intel E7501 Northbridge",
};

2
src/northbridge/intel/i855pm/chip.h
View File

@ -2,4 +2,4 @@ struct northbridge_intel_i855pm_config
{
};
extern struct chip_control northbridge_intel_i855pm_control;
extern struct chip_operations northbridge_intel_i855pm_control;

33
src/northbridge/intel/i855pm/northbridge.c
View File

@ -113,38 +113,7 @@ struct mem_range *sizeram(void)
return mem;
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
#if 0
static void northbridge_init(struct chip *chip, enum chip_pass pass)
{
struct northbridge_intel_i855pm_config *conf =
(struct northbridge_intel_i855pm_config *)chip->chip_info;
switch (pass) {
case CONF_PASS_PRE_PCI:
break;
case CONF_PASS_POST_PCI:
break;
case CONF_PASS_PRE_BOOT:
break;
default:
/* nothing yet */
break;
}
}
#endif
struct chip_control northbridge_intel_i855pm_control = {
.enumerate = enumerate,
// .enable = northbridge_init,
struct chip_operations northbridge_intel_i855pm_control = {
.name = "intel i855pm Northbridge",
};

2
src/northbridge/transmeta/tm5800/chip.h
View File

@ -2,4 +2,4 @@ struct northbridge_transmeta_tm5800_config
{
};
extern struct chip_control northbridge_transmeta_tm5800_control;
extern struct chip_operations northbridge_transmeta_tm5800_control;

9
src/northbridge/transmeta/tm5800/northbridge.c
View File

@ -118,13 +118,6 @@ static struct pci_driver mcf0_driver __pci_driver = {
.device = 0x1100,
};
static void enumerate(struct chip *chip)
{
chip_enumerate(chip);
chip->dev->ops = &northbridge_operations;
}
struct chip_control northbridge_amd_tm5800_control = {
struct chip_operations northbridge_amd_tm5800_control = {
.name = "Transmeta tm5800 Northbridge",
.enumerate = enumerate,
};

2
src/northbridge/via/vt8601/chip.h
View File

@ -2,4 +2,4 @@ struct northbridge_via_vt8601_config
{
};
extern struct chip_control northbridge_via_vt8601_control;
extern struct chip_operations northbridge_via_vt8601_control;

9
src/northbridge/via/vt8601/northbridge.c
View File

@ -63,12 +63,6 @@ struct mem_range *sizeram(void)
return mem;
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
/*
* This fixup is based on capturing values from an Award bios. Without
@ -114,8 +108,7 @@ static void northbridge_init(struct chip *chip, enum chip_pass pass)
}
}
struct chip_control northbridge_via_vt8601_control = {
.enumerate = enumerate,
struct chip_operations northbridge_via_vt8601_control = {
.enable = northbridge_init,
.name = "VIA vt8601 Northbridge",
};

2
src/northbridge/via/vt8623/chip.h
View File

@ -2,4 +2,4 @@ struct northbridge_via_vt8623_config
{
};
extern struct chip_control northbridge_via_vt8623_control;
extern struct chip_operations northbridge_via_vt8623_control;

9
src/northbridge/via/vt8623/northbridge.c
View File

@ -65,12 +65,6 @@ struct mem_range *sizeram(void)
return mem;
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
/*
* This fixup is based on capturing values from an Award bios. Without
@ -164,8 +158,7 @@ static void northbridge_init(struct chip *chip, enum chip_pass pass)
}
}
struct chip_control northbridge_via_vt8623_control = {
.enumerate = enumerate,
struct chip_operations northbridge_via_vt8623_control = {
.enable = northbridge_init,
.name = "VIA vt8623 Northbridge",
};

1
src/pc80/isa-dma.c
View File

@ -1,4 +1,5 @@
#include <arch/io.h>
#include <pc80/isa-dma.h>
/* DMA controller registers */
#define DMA1_CMD_REG 0x08 /* command register (w) */

2
src/pc80/vgachip.h
View File

@ -1,7 +1,7 @@
#ifndef _PC80_VGABIOS
#define _PC80_VGABIOS
extern struct chip_control pc80_vgabios_control;
extern struct chip_operations pc80_vgabios_control;
struct pc80_vgabios_config {
int nothing;

48
src/southbridge/amd/amd8111/amd8111.c
View File

@ -9,31 +9,32 @@ void amd8111_enable(device_t dev)
device_t lpc_dev;
device_t bus_dev;
unsigned index;
uint32_t dword;
uint16_t reg_old, reg;
uint8_t byte;
unsigned reg_old, reg;
/* See if we are on the behind the amd8111 pci bridge */
bus_dev = dev->bus->dev;
if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
(bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) {
(bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
{
unsigned devfn;
devfn = bus_dev->path.u.pci.devfn + (1 << 3);
lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8;
if (dev->path.u.pci.devfn == 2) { /* EHCI */
index = 16;
}
} else {
unsigned devfn;
devfn = (dev->path.u.pci.devfn) & ~7;
lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
index = dev->path.u.pci.devfn & 7;
}
if ((!lpc_dev) || (index >= 16)) {
if ((!lpc_dev) || (index >= 17)) {
return;
}
if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) ||
(lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) {
(lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA))
{
uint32_t id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) {
@ -41,22 +42,7 @@ void amd8111_enable(device_t dev)
}
}
/* Now read the vendor and device id */
dword= pci_read_config32(dev, PCI_VENDOR_ID);
#if 0
printk_debug(" %s dev->vendor= %04x, dev->device= %04x, id = %08x\n", dev_path(dev), dev->vendor, dev->device, dword);
#endif
if (dword == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_USB2 << 16))) {
if(!dev->enabled) {
byte = pci_read_config8(lpc_dev, 0x47);
byte |= (1<<7);
pci_write_config8(lpc_dev, 0x47, byte);
return;
}
}
if (index < 16) {
reg = reg_old = pci_read_config16(lpc_dev, 0x48);
reg &= ~(1 << index);
if (dev->enabled) {
@ -65,10 +51,20 @@ void amd8111_enable(device_t dev)
if (reg != reg_old) {
pci_write_config16(lpc_dev, 0x48, reg);
}
}
else if (index == 16) {
reg = reg_old = pci_read_config8(lpc_dev, 0x47);
reg &= ~(1 << 7);
if (!dev->enabled) {
reg |= (1 << 7);
}
if (reg != reg_old) {
pci_write_config8(lpc_dev, 0x47, reg);
}
}
}
struct chip_operations southbridge_amd_amd8111_ops = {
.name = "AMD 8111 Southbridge",
.name = "AMD 8111",
.enable_dev = amd8111_enable,
};

15
src/southbridge/amd/amd8111/amd8111_ac97.c
View File

@ -8,14 +8,24 @@
#include <device/pci_ops.h>
#include "amd8111.h"
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x2c,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations ac97audio_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
// .enable = amd8111_enable,
.enable = amd8111_enable,
.init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
static struct pci_driver ac97audio_driver __pci_driver = {
@ -29,9 +39,10 @@ static struct device_operations ac97modem_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
// .enable = amd8111_enable,
.enable = amd8111_enable,
.init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
static struct pci_driver ac97modem_driver __pci_driver = {

118
src/southbridge/amd/amd8111/amd8111_acpi.c
View File

@ -3,10 +3,12 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/smbus.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
#include <arch/io.h>
#include "amd8111.h"
#include "amd8111_smbus.h"
#define PREVIOUS_POWER_STATE 0x43
#define MAINBOARD_POWER_OFF 0
@ -19,6 +21,51 @@
#endif
static int lsmbus_recv_byte(device_t dev)
{
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
res = find_resource(dev->bus->dev, 0x20);
return do_smbus_recv_byte(res->base, device);
}
static int lsmbus_send_byte(device_t dev, uint8_t val)
{
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
res = find_resource(dev->bus->dev, 0x20);
return do_smbus_send_byte(res->base, device, val);
}
static int lsmbus_read_byte(device_t dev, uint8_t address)
{
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
res = find_resource(dev->bus->dev, 0x20);
return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
{
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
res = find_resource(dev->bus->dev, 0x20);
return do_smbus_write_byte(res->base, device, address, val);
}
static void acpi_init(struct device *dev)
{
uint8_t byte;
@ -29,29 +76,26 @@ static void acpi_init(struct device *dev)
#if 0
printk_debug("ACPI: disabling NMI watchdog.. ");
pci_read_config_byte(dev, 0x49, &byte);
pci_write_config_byte(dev, 0x49, byte | (1<<2));
byte = pci_read_config8(dev, 0x49);
pci_write_config8(dev, 0x49, byte | (1<<2));
pci_read_config_byte(dev, 0x41, &byte);
pci_write_config_byte(dev, 0x41, byte | (1<<6)|(1<<2));
byte = pci_read_config8(dev, 0x41);
pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2));
/* added from sourceforge */
pci_read_config_byte(dev, 0x48, &byte);
pci_write_config_byte(dev, 0x48, byte | (1<<3));
byte = pci_read_config8(dev, 0x48);
pci_write_config8(dev, 0x48, byte | (1<<3));
printk_debug("done.\n");
printk_debug("ACPI: Routing IRQ 12 to PS2 port.. ");
pci_read_config_word(dev, 0x46, &word);
pci_write_config_word(dev, 0x46, word | (1<<9));
word = pci_read_config16(dev, 0x46);
pci_write_config16(dev, 0x46, word | (1<<9));
printk_debug("done.\n");
printk_debug("ACPI: setting PM class code.. ");
pci_write_config_dword(dev, 0x60, 0x06800000);
printk_debug("done.\n");
#endif
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
@ -78,12 +122,13 @@ static void acpi_init(struct device *dev)
static void acpi_read_resources(device_t dev)
{
struct resource *resource;
/* Handle the generic bars */
pci_dev_read_resources(dev);
if ((dev->resources + 1) < MAX_RESOURCES) {
struct resource *resource = &dev->resource[dev->resources];
dev->resources++;
/* Add the ACPI/SMBUS bar */
resource = new_resource(dev, 0x58);
resource->base = 0;
resource->size = 256;
resource->align = log2(256);
@ -91,20 +136,49 @@ static void acpi_read_resources(device_t dev)
resource->limit = 65536;
resource->flags = IORESOURCE_IO;
resource->index = 0x58;
}
else {
printk_err("%s Unexpected resource shortage\n",
dev_path(dev));
}
}
static void acpi_enable_resources(device_t dev)
{
uint8_t byte;
/* Enable the generic pci resources */
pci_dev_enable_resources(dev);
/* Enable the ACPI/SMBUS Bar */
byte = pci_read_config8(dev, 0x41);
byte |= (1 << 7);
pci_write_config8(dev, 0x41, byte);
/* Set the class code */
pci_write_config32(dev, 0x60, 0x06800000);
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x7c,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct smbus_bus_operations lops_smbus_bus = {
.recv_byte = lsmbus_recv_byte,
.send_byte = lsmbus_send_byte,
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
};
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations acpi_ops = {
.read_resources = acpi_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable_resources = acpi_enable_resources,
.init = acpi_init,
.scan_bus = 0,
// .enable = amd8111_enable,
.scan_bus = scan_static_bus,
.enable = amd8111_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
static struct pci_driver acpi_driver __pci_driver = {

117
src/southbridge/amd/amd8111/amd8111_early_smbus.c
View File

@ -1,14 +1,7 @@
#include "amd8111_smbus.h"
#define SMBUS_IO_BASE 0x0f00
#define SMBGSTATUS 0xe0
#define SMBGCTL 0xe2
#define SMBHSTADDR 0xe4
#define SMBHSTDAT 0xe6
#define SMBHSTCMD 0xe8
#define SMBHSTFIFO 0xe9
#define SMBUS_TIMEOUT (100*1000*10)
static void enable_smbus(void)
{
device_t dev;
@ -25,114 +18,22 @@ static void enable_smbus(void)
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
}
static inline void smbus_delay(void)
static int smbus_recv_byte(unsigned device)
{
outb(0x80, 0x80);
return do_smbus_recv_byte(SMBUS_IO_BASE, device);
}
static int smbus_wait_until_ready(void)
static int smbus_send_byte(unsigned device, unsigned char val)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned short val;
smbus_delay();
val = inw(SMBUS_IO_BASE + SMBGSTATUS);
if ((val & 0x800) == 0) {
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(SMBUS_IO_BASE + SMBGSTATUS),
SMBUS_IO_BASE + SMBGSTATUS);
}
} while(--loops);
return loops?0:-2;
}
static int smbus_wait_until_done(void)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned short val;
smbus_delay();
val = inw(SMBUS_IO_BASE + SMBGSTATUS);
if (((val & 0x8) == 0) | ((val & 0x437) != 0)) {
break;
}
} while(--loops);
return loops?0:-3;
return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
static int smbus_read_byte(unsigned device, unsigned address)
{
unsigned char global_control_register;
unsigned char global_status_register;
unsigned char byte;
if (smbus_wait_until_ready() < 0) {
return -2;
}
/* setup transaction */
/* disable interrupts */
outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), SMBUS_IO_BASE + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x2), SMBUS_IO_BASE + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
/* clear the data word...*/
outw(0, SMBUS_IO_BASE + SMBHSTDAT);
/* start the command */
outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done() < 0) {
return -3;
}
global_status_register = inw(SMBUS_IO_BASE + SMBGSTATUS);
/* read results of transaction */
byte = inw(SMBUS_IO_BASE + SMBHSTDAT) & 0xff;
if (global_status_register != (1 << 4)) {
return -1;
}
return byte;
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
if (smbus_wait_until_ready() < 0) {
return;
}
/* by LYH */
outb(0x37,SMBUS_IO_BASE + SMBGSTATUS);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
/* data to send */
outb(val, SMBUS_IO_BASE + SMBHSTDAT);
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* start the command */
outb(0xa, SMBUS_IO_BASE + SMBGCTL);
/* poll for transaction completion */
smbus_wait_until_done();
return;
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}

6
src/southbridge/amd/amd8111/amd8111_enable_rom.c
View File

@ -4,12 +4,12 @@ static void amd8111_enable_rom(void)
unsigned char byte;
device_t dev;
/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
/* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */
/* Locate the amd8111 */
dev = pci_locate_device(PCI_ID(0x1022, 0x7468), 0);
/* Set the 4MB enable bit bit */
/* Set the 5MB enable bits */
byte = pci_read_config8(dev, 0x43);
byte |= 0x80;
byte |= 0xC0;
pci_write_config8(dev, 0x43, byte);
}

18
src/southbridge/amd/amd8111/amd8111_ide.c
View File

@ -7,21 +7,21 @@
static void ide_init(struct device *dev)
{
struct southbridge_amd_amd8111_config *conf;
/* Enable ide devices so the linux ide driver will work */
uint16_t word;
uint8_t byte;
int enable_a=1, enable_b=1;
conf = dev->chip_info;
word = pci_read_config16(dev, 0x40);
/* Ensure prefetch is disabled */
word &= ~((1 << 15) | (1 << 13));
if (enable_b) {
if (conf->ide1_enable) {
/* Enable secondary ide interface */
word |= (1<<0);
printk_debug("IDE1 ");
}
if (enable_a) {
if (conf->ide0_enable) {
/* Enable primary ide interface */
word |= (1<<1);
printk_debug("IDE0 ");
@ -40,12 +40,22 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, 0x42, word);
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
.enable = amd8111_enable,
.ops_pci = &lops_pci
};
static struct pci_driver ide_driver __pci_driver = {

42
src/southbridge/amd/amd8111/amd8111_lpc.c
View File

@ -7,10 +7,9 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include "amd8111.h"
void isa_dma_init(void); /* from /pc80/isa-dma.c */
#define NMI_OFF 0
struct ioapicreg {
@ -158,43 +157,36 @@ static void lpc_init(struct device *dev)
static void amd8111_lpc_read_resources(device_t dev)
{
unsigned int reg;
struct resource *res;
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
/* Find my place in the resource list */
reg = dev->resources;
/* Add an extra subtractive resource for both memory and I/O */
dev->resource[reg].base = 0;
dev->resource[reg].size = 0;
dev->resource[reg].align = 0;
dev->resource[reg].gran = 0;
dev->resource[reg].limit = 0;
dev->resource[reg].flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
dev->resource[reg].index = 0;
reg++;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
dev->resource[reg].base = 0;
dev->resource[reg].size = 0;
dev->resource[reg].align = 0;
dev->resource[reg].gran = 0;
dev->resource[reg].limit = 0;
dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
dev->resource[reg].index = 0;
reg++;
dev->resources = reg;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations lpc_ops = {
.read_resources = amd8111_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
// .enable = amd8111_enable,
.enable = amd8111_enable,
.ops_pci = &lops_pci,
};
static struct pci_driver lpc_driver __pci_driver = {

2
src/southbridge/amd/amd8111/amd8111_nic.c
View File

@ -13,7 +13,7 @@ static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
// .enable = amd8111_enable,
.enable = amd8111_enable,
.init = 0,
.scan_bus = 0,
};

5
src/southbridge/amd/amd8111/amd8111_pci.c
View File

@ -45,12 +45,17 @@ static void pci_init(struct device *dev)
pci_write_config32(dev, 0x1c, dword);
}
static struct pci_operations lops_pci = {
.set_subsystem = 0,
};
static struct device_operations pci_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.scan_bus = pci_scan_bridge,
.ops_pci = &lops_pci,
};
static struct pci_driver pci_driver __pci_driver = {

124
src/southbridge/amd/amd8111/amd8111_smbus.c
View File

@ -1,96 +1,42 @@
#include <smbus.h>
#include <pci.h>
/*
* (C) 2004 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/chip.h>
#include <device/smbus.h>
#include <arch/io.h>
#include "amd8111.h"
#define PM_BUS 0
#define PM_DEVFN PCI_DEVFN(0x7,3)
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
#define SMBHSTCMD 3
#define SMBHSTADD 4
#define SMBHSTDAT0 5
#define SMBHSTDAT1 6
#define SMBBLKDAT 7
void smbus_enable(void)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
unsigned char byte;
#if 0
/* iobase addr */
pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x90, SMBUS_IO_BASE | 1);
/* smbus enable */
pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0xd2, (0x4 << 1) | 1);
/* iospace enable */
pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
#endif
/* Set PMIOEN, leaving default address 0xDD00 in 0x58 */
byte=pcibios_read_config_byte(0,PCI_DEVFN(0x7,3), 0x41);
pcibios_write_config_byte(0,PCI_DEVFN(0x7,3), byte | 0x80 );
/* cont reading 207 */
pci_write_config32(dev, 0x44,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
void smbus_setup(void)
{
outb(0, SMBUS_IO_BASE + SMBHSTSTAT);
}
static struct smbus_bus_operations lops_smbus_bus = {
/* I haven't seen the 2.0 SMBUS controller used yet. */
};
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations smbus_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_static_bus,
.enable = amd8111_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
static void smbus_wait_until_ready(void)
{
while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
/* nop */
}
}
static void smbus_wait_until_done(void)
{
unsigned char byte;
do {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
while((byte &1) == 1);
while( (byte & ~1) == 0) {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
}
int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
{
unsigned char host_status_register;
unsigned char byte;
smbus_wait_until_ready();
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* clear the data byte...*/
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start the command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for transaction completion */
smbus_wait_until_done();
host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
/* read results of transaction */
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
*result = byte;
return host_status_register != 0x02;
}
static struct pci_driver smbus_driver __pci_driver = {
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_8111_SMB,
};

224
src/southbridge/amd/amd8111/amd8111_smbus.h Normal file
View File

@ -0,0 +1,224 @@
#include <device/smbus_def.h>
#define SMBGSTATUS 0xe0
#define SMBGCTL 0xe2
#define SMBHSTADDR 0xe4
#define SMBHSTDAT 0xe6
#define SMBHSTCMD 0xe8
#define SMBHSTFIFO 0xe9
#define SMBUS_TIMEOUT (100*1000*10)
#define SMBUS_STATUS_MASK 0xfbff
static inline void smbus_delay(void)
{
outb(0x80, 0x80);
}
static int smbus_wait_until_ready(unsigned smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned short val;
smbus_delay();
val = inw(smbus_io_base + SMBGSTATUS);
if ((val & 0x800) == 0) {
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(smbus_io_base + SMBGSTATUS),
smbus_io_base + SMBGSTATUS);
}
} while(--loops);
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
static int smbus_wait_until_done(unsigned smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned short val;
smbus_delay();
val = inw(smbus_io_base + SMBGSTATUS);
if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
break;
}
} while(--loops);
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
{
unsigned global_status_register;
unsigned byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
/* set the command/address... */
outb(0, smbus_io_base + SMBHSTCMD);
/* set up for a send byte */
outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
/* set the data word...*/
outw(0, smbus_io_base + SMBHSTDAT);
/* start the command */
outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
global_status_register = inw(smbus_io_base + SMBGSTATUS);
/* read results of transaction */
byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
return SMBUS_ERROR;
}
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned value)
{
unsigned global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
/* set the command/address... */
outb(0, smbus_io_base + SMBHSTCMD);
/* set up for a send byte */
outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
/* set the data word...*/
outw(value, smbus_io_base + SMBHSTDAT);
/* start the command */
outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
global_status_register = inw(smbus_io_base + SMBGSTATUS);
if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
return SMBUS_ERROR;
}
return 0;
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
{
unsigned global_status_register;
unsigned byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
/* set the command/address... */
outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
/* set up for a byte data read */
outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
/* clear the data word...*/
outw(0, smbus_io_base + SMBHSTDAT);
/* start the command */
outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
global_status_register = inw(smbus_io_base + SMBGSTATUS);
/* read results of transaction */
byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
return SMBUS_ERROR;
}
return byte;
}
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
{
unsigned global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
/* set up for a byte data write */ /* FIXME */
outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
/* write the data word...*/
outw(val, smbus_io_base + SMBHSTDAT);
/* start the command */
outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
global_status_register = inw(smbus_io_base + SMBGSTATUS);
if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
return SMBUS_ERROR;
}
return 0;
}

47
src/southbridge/amd/amd8111/amd8111_usb.c
View File

@ -1,39 +1,42 @@
/*
* (C) 2004 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/chip.h>
#include <device/smbus.h>
#include <arch/io.h>
#include "amd8111.h"
static void usb_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
uint32_t cmd;
#if 0
printk_debug("USB: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
printk_debug("done.\n");
#endif
pci_write_config32(dev, 0x44,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct device_operations usb_ops = {
static struct smbus_bus_operations lops_smbus_bus = {
/* I haven't seen the 2.0 SMBUS controller used yet. */
};
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations smbus_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = usb_init,
.scan_bus = 0,
// .enable = amd8111_enable,
.init = 0,
.scan_bus = scan_static_bus,
.enable = amd8111_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
static struct pci_driver usb_driver __pci_driver = {
.ops = &usb_ops,
static struct pci_driver smbus_driver __pci_driver = {
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_8111_USB,
.device = PCI_DEVICE_ID_AMD_8111_SMB,
};

13
src/southbridge/amd/amd8111/amd8111_usb2.c
View File

@ -23,13 +23,24 @@ static void usb2_init(struct device *dev)
#endif
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations usb2_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = usb2_init,
.scan_bus = 0,
// .enable = amd8111_enable,
.enable = amd8111_enable,
.ops_pci = &lops_pci,
};
static struct pci_driver usb2_driver __pci_driver = {

3
src/southbridge/amd/amd8111/chip.h
View File

@ -3,7 +3,10 @@
struct southbridge_amd_amd8111_config
{
unsigned int ide0_enable : 1;
unsigned int ide1_enable : 1;
};
struct chip_operations;
extern struct chip_operations southbridge_amd_amd8111_ops;

11
src/southbridge/amd/amd8131/amd8131_bridge.c
View File

@ -1,5 +1,5 @@
/*
* (C) 2003 Linux Networx
* (C) 2003-2004 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
@ -106,13 +106,11 @@ static void ioapic_enable(device_t dev)
value &= ~((1 << 1) | (1 << 0));
}
pci_write_config32(dev, 0x44, value);
/* We have to enable MEM and Bus Master for IOAPIC */
value = pci_read_config32(dev, 0x4);
value |= 6;
pci_write_config32(dev, 0x4, value);
}
static struct pci_operations pci_ops_pci_dev = {
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations ioapic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
@ -120,6 +118,7 @@ static struct device_operations ioapic_ops = {
.init = 0,
.scan_bus = 0,
.enable = ioapic_enable,
.ops_pci = &pci_ops_pci_dev,
};
static struct pci_driver ioapic_driver __pci_driver = {

2
src/southbridge/intel/i82801dbm/i82801dbm.c
View File

@ -50,7 +50,7 @@ void i82801dbm_enable(device_t dev)
}
struct chip_control southbridge_intel_i82801dbm_control = {
struct chip_operations southbridge_intel_i82801dbm_control = {
.name = "Intel 82801dbm Southbridge",
.enable_dev = i82801dbm_enable,
};

2
src/southbridge/intel/i82801er/i82801er.c
View File

@ -50,7 +50,7 @@ void i82801er_enable(device_t dev)
}
struct chip_control southbridge_intel_i82801er_control = {
struct chip_operations southbridge_intel_i82801er_control = {
.name = "Intel 82801er Southbridge",
.enable_dev = i82801er_enable,
};

2
src/southbridge/ricoh/rl5c476/chip.h
View File

@ -1,7 +1,7 @@
#ifndef _SOUTHBRIDGE_RICOH_RL5C476
#define _SOUTHBRIDGE_RICOH_RL5C476
extern struct chip_control southbridge_ricoh_rl5c476_control;
extern struct chip_operations southbridge_ricoh_rl5c476_control;
struct southbridge_ricoh_rl5c476_config {
int num;

60
src/southbridge/ricoh/rl5c476/rl5c476.c
View File

@ -77,22 +77,16 @@ dump_south(void)
}
static void rl5c476_init(struct southbridge_rl5c476_config *conf)
static void rl5c476_init(device_t dev)
{
//unsigned char enables;
device_t dev;
pc16reg_t *pc16;
int i;
printk_debug("rl5c476 init\n");
#error "FIXME implement carbus bridge support"
#error "FIXME this code is close to a but the conversion needs more work"
/* cardbus controller function 1 for CF Socket */
dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, 0);
if (!dev ){
// probably an epia-m rather than mii
printk_debug("No rl5c476 found\n");
return;
}
printk_debug("rl5c476 init\n");
/* setup pci header manually because 'pci_device.c' doesn't know how to handle
* pci to cardbus bridges - (header type 2 I think)
@ -214,41 +208,21 @@ static void rl5c476_init(struct southbridge_rl5c476_config *conf)
}
static void southbridge_init(struct chip *chip, enum chip_pass pass)
{
static struct device_operations ricoh_rl5c476_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.inti = rl5c476_init,
.scan_bus = pci_scan_bridge,
};
struct southbridge_rl5c476_config *conf =
(struct southbridge_rl5c476_config *)chip->chip_info;
static struct pci_driver ricoh_rl5c476_driver __pci_driver = {
.ops = &ricoh_rl5c476_ops,
.vendor = PCI_VENDOR_ID_RICOH,
.device = PCI_DEVICE_ID_RICOH_RL5C476,
};
switch (pass) {
case CONF_PASS_PRE_PCI:
//rl5c476_pci_enable(conf);
break;
case CONF_PASS_POST_PCI:
rl5c476_init(conf);
break;
case CONF_PASS_PRE_BOOT:
//dump_south();
break;
default:
/* nothing yet */
break;
}
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
struct chip_control southbridge_ricoh_rl5c476_control = {
.enumerate = enumerate,
struct chip_operations southbridge_ricoh_rl5c476_control = {
.enable = southbridge_init,
.name = "RICOH RL5C476"
};

2
src/southbridge/via/vt8231/chip.h
View File

@ -1,7 +1,7 @@
#ifndef _SOUTHBRIDGE_VIA_VT8231
#define _SOUTHBRIDGE_VIA_VT8231
extern struct chip_control southbridge_via_vt8231_control;
extern struct chip_operations southbridge_via_vt8231_control;
struct southbridge_via_vt8231_config {
/* PCI function enables */

10
src/southbridge/via/vt8231/vt8231.c
View File

@ -449,15 +449,7 @@ static void southbridge_init(struct chip *chip, enum chip_pass pass)
}
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
struct chip_control southbridge_via_vt8231_control = {
.enumerate = enumerate,
struct chip_operations southbridge_via_vt8231_control = {
.enable = southbridge_init,
.name = "VIA vt8231"
};

2
src/southbridge/via/vt8235/chip.h
View File

@ -1,7 +1,7 @@
#ifndef _SOUTHBRIDGE_VIA_VT8235
#define _SOUTHBRIDGE_VIA_VT8235
extern struct chip_control southbridge_via_vt8235_control;
extern struct chip_operations southbridge_via_vt8235_control;
struct southbridge_via_vt8235_config {
/* PCI function enables */

10
src/southbridge/via/vt8235/vt8235.c
View File

@ -557,15 +557,7 @@ static void southbridge_init(struct chip *chip, enum chip_pass pass)
}
}
static void enumerate(struct chip *chip)
{
extern struct device_operations default_pci_ops_bus;
chip_enumerate(chip);
chip->dev->ops = &default_pci_ops_bus;
}
struct chip_control southbridge_via_vt8235_control = {
.enumerate = enumerate,
struct chip_operations southbridge_via_vt8235_control = {
.enable = southbridge_init,
.name = "VIA vt8235"
};

2
src/southbridge/winbond/w83c553/chip.h
View File

@ -1,7 +1,7 @@
#ifndef _SOUTHBRIDGE_WINBOND_W83C553
#define _SOUTHBRIDGE_WINBOND_W83C553
extern struct chip_control southbridge_winbond_w83c553_control;
extern struct chip_operations southbridge_winbond_w83c553_control;
struct southbridge_winbond_w83c553_config {
};

2
src/superio/NSC/pc87366/chip.h
View File

@ -5,7 +5,7 @@
#define SIO_COM2_BASE 0x2F8
#endif
extern struct chip_control superio_NSC_pc87366_control;
extern struct chip_operations superio_NSC_pc87366_control;
#include <pc80/keyboard.h>
#include <uart8250.h>

20
src/superio/NSC/pc87366/superio.c
View File

@ -23,19 +23,19 @@ static void init(device_t dev)
if (!dev->enabled) {
return;
}
conf = dev->chip->chip_info;
conf = dev->chip_info;
switch(dev->path.u.pnp.device) {
case PC87366_SP1:
res0 = get_resource(dev, PNP_IDX_IO0);
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case PC87366_SP2:
res0 = get_resource(dev, PNP_IDX_IO0);
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case PC87366_KBCK:
res0 = get_resource(dev, PNP_IDX_IO0);
res1 = get_resource(dev, PNP_IDX_IO1);
res0 = find_resource(dev, PNP_IDX_IO0);
res1 = find_resource(dev, PNP_IDX_IO1);
init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
break;
}
@ -64,13 +64,13 @@ static struct pnp_info pnp_dev_info[] = {
};
static void enumerate(struct chip *chip)
static void enable_dev(struct device *dev)
{
pnp_enumerate(chip, sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
&pnp_ops, pnp_dev_info);
pnp_enable_device(dev, &pnp_ops,
sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
}
struct chip_control superio_NSC_pc87366_control = {
.enumerate = enumerate,
struct chip_operations superio_NSC_pc87366_control = {
.enable_dev = enable_dev,
.name = "NSC 87366"
};

8
src/superio/NSC/pc97307/chip.h
View File

@ -14,9 +14,13 @@
#define SIO_COM2_BASE 0x2F8
#endif
extern struct chip_control superio_NSC_pc97307_control;
extern struct chip_operations superio_NSC_pc97307_control;
#include <pc80/keyboard.h>
#include <uart8250.h>
struct superio_NSC_pc97307_config {
int port;
struct uart8250 com1, com2;
struct pc_keyboard keyboard;
};
#endif /* _SUPERIO_NSC_PC97307 */

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