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soc/intel/meteoerlake: set power limits dynamically 

Set power limit values dynamically based on Meteor Lake
CPU TDP and PCI ID of SKU.

BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values for 15W SKU on Rex board

Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Sumeet R Pawnikar 2023-04-13 22:02:01 +05:30 committed by Felix Held
parent 3810705ef0
commit dbf132cc1e
3 changed files with 62 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/soc/intel/meteorlake/chip.h
View File

@ -4,6 +4,7 @@
#define _SOC_CHIP_H_
#include <drivers/i2c/designware/dw_i2c.h>
#include <device/pci_ids.h>
#include <gpio.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gspi.h>
@ -19,13 +20,24 @@
/* Types of different SKUs */
enum soc_intel_meteorlake_power_limits {
MTL_P_POWER_LIMITS_1,
MTL_P_POWER_LIMITS_2,
MTL_P_POWER_LIMITS_3,
MTL_P_POWER_LIMITS_4,
MTL_P_282_CORE,
MTL_POWER_LIMITS_COUNT
};
/* TDP values for different SKUs */
enum soc_intel_meteorlake_cpu_tdps {
TDP_15W = 15
};
/* Mapping of different SKUs based on CPU ID and TDP values */
static const struct {
unsigned int cpu_id;
enum soc_intel_meteorlake_power_limits limits;
enum soc_intel_meteorlake_cpu_tdps cpu_tdp;
} cpuid_to_mtl[] = {
{ PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_CORE, TDP_15W },
};
/* Types of display ports */
enum ddi_ports {
DDI_PORT_A,

11
src/soc/intel/meteorlake/chipset.cb
View File

@ -2,15 +2,10 @@ chip soc/intel/meteorlake
device cpu_cluster 0 on end
#FIXME: update values for MTL and enable override in systemagent.c
register "power_limits_config[MTL_P_POWER_LIMITS_2]" = "{
register "power_limits_config[MTL_P_282_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
}"
register "power_limits_config[MTL_P_POWER_LIMITS_1]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_pl2_override = 57,
.tdp_pl4 = 114,
}"
# NOTE: if any variant wants to override this value, use the same format

75
src/soc/intel/meteorlake/systemagent.c
View File

@ -5,7 +5,6 @@
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <delay.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/msr.h>
@ -145,52 +144,64 @@ void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count);
}
/*
* SoC implementation
*
* Perform System Agent Initialization during Ramstage phase.
*/
void soc_systemagent_init(struct device *dev)
static void configure_tdp(struct device *dev)
{
struct soc_power_limits_config *soc_config;
struct device *sa;
uint16_t sa_pci_id;
u8 tdp;
size_t i;
bool config_tdp = false;
config_t *config;
/* Enable Power Aware Interrupt Routing */
enable_power_aware_intr();
config = config_of_soc();
/* Get System Agent PCI ID */
sa = pcidev_path_on_root(PCI_DEVFN_ROOT);
sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
/* Choose a power limits configuration based on the SoC SKU type,
* differentiated here based on SA PCI ID. */
switch (sa_pci_id) {
case PCI_DID_INTEL_MTL_P_ID_1:
soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_1];
break;
case PCI_DID_INTEL_MTL_P_ID_2:
soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_2];
break;
case PCI_DID_INTEL_MTL_P_ID_3:
soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_3];
break;
case PCI_DID_INTEL_MTL_P_ID_4:
soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_4];
break;
default:
printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n",
sa_pci_id);
if (sa_pci_id == 0xFFFF) {
printk(BIOS_WARNING, "Unknown SA PCI Device!\n");
return;
}
/* Remove once commented line below is enabled */
(void)soc_config;
/* UPDATEME: Need to enable later */
//set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
tdp = get_cpu_tdp();
/*
* Choose power limits configuration based on the CPU SA PCI ID and
* CPU TDP value.
*/
for (i = 0; i < ARRAY_SIZE(cpuid_to_mtl); i++) {
if (sa_pci_id == cpuid_to_mtl[i].cpu_id &&
tdp == cpuid_to_mtl[i].cpu_tdp) {
soc_config = &config->power_limits_config[cpuid_to_mtl[i].limits];
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
config_tdp = true;
printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n",
sa_pci_id);
break;
}
}
if (!config_tdp) {
printk(BIOS_WARNING, "Skipped power limits configuration for SA PCI ID: 0x%4x\n",
sa_pci_id);
return;
}
}
/*
* SoC implementation
*
* Perform System Agent Initialization during ramstage phase.
*/
void soc_systemagent_init(struct device *dev)
{
/* Enable Power Aware Interrupt Routing */
enable_power_aware_intr();
/* Configure TDP */
configure_tdp(dev);
}
uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)