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mb/intel/tglrvp: Enable recovery in TGL RVP 

Share "EC in RW" GPIO with depthcharge. Also we define the CONFIGS
needed CHROME, CHROME_EC and use the chrome lid and recovery.

BUG=None
BRANCH=None
TEST=Build and boot TGL RVP. Check recovery works with
crossystem recovery_request.

Change-Id: I1e88200e3f8418e5b0ab39ac65ed1b3545ce111e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
This commit is contained in:
Shaunak Saha 2020-04-29 13:19:44 -07:00 committed by Patrick Georgi
parent 1866a8cba4
commit dbf6f688aa
2 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/intel/tglrvp/Kconfig
View File

@ -16,10 +16,15 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_TIGERLAKE select SOC_INTEL_TIGERLAKE
select INTEL_LPSS_UART_FOR_CONSOLE select INTEL_LPSS_UART_FOR_CONSOLE
select DRIVERS_INTEL_ISH select DRIVERS_INTEL_ISH
select EC_ACPI
config CHROMEOS config CHROMEOS
bool bool
default y default y
select EC_GOOGLE_CHROMEEC_SWITCHES if TGL_CHROME_EC
select GBB_FLAG_FORCE_MANUAL_RECOVERY
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_USB
@ -68,9 +73,9 @@ choice TGL_EC
config TGL_CHROME_EC config TGL_CHROME_EC
bool "Chrome EC" bool "Chrome EC"
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_BOARDID
select EC_ACPI
config TGL_INTEL_EC config TGL_INTEL_EC
bool "Intel EC" bool "Intel EC"
@ -81,8 +86,6 @@ endchoice
config VBOOT config VBOOT
select VBOOT_LID_SWITCH select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA select VBOOT_MOCK_SECDATA
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config UART_FOR_CONSOLE config UART_FOR_CONSOLE
int int

4
src/mainboard/intel/tglrvp/chromeos.c
View File

@ -12,10 +12,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
{-1, ACTIVE_HIGH, 0, "EC in RW"},
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
int get_lid_switch(void) int get_lid_switch(void)
{ {
/* Lid always open */ /* Lid always open */
@ -27,6 +29,8 @@ int get_recovery_mode_switch(void)
return 0; return 0;
} }
#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
int get_write_protect_state(void) int get_write_protect_state(void)
{ {
/* No write protect */ /* No write protect */