veyron: Turn off SD card power in romstage
The only way to reliably reset an SD card in an unknown state is by power-cycling. Since a kernel may crash and reboot at any point, SD cards may be left in one of them fancy high-throughput modes that depthcharge (or, in fact, a newly booting kernel without prior knowledge) doesn't support, so we need to reset the card on every boot. This patch adds support to turn off an RK808 regulator completely and uses that to turn off SD card power rails in early romstage. The time until configure_sdmmc() in ramstage turns them back on should be more than enough to drain the power rail for an effective power-cycle. BRANCH=None BUG=chrome-os-partner:34289 TEST=Booted a Pinky from SD card, noticed that it works before and after this patch. Change-Id: Iaa5f7adaa59da69a964785c5e369ad73c6620224 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 95fba21907f1f3f686cb5a95b993736247db8f96 Original-Change-Id: I904b2d23ca35f765c000f9bee7637044f674eff9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/233713 Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Original-Tested-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9626 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
parent
13cee14c9c
commit
dbfa9d5e8d
src
mainboard/google
veyron_jerry
veyron_mighty
veyron_pinky
soc/rockchip/rk3288
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@ -52,6 +52,7 @@ static void configure_sdmmc(void)
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/* use sdmmc0 io, disable JTAG function */
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writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
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/* Note: these power rail definitions are copied in romstage.c */
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rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
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rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
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@ -31,6 +31,7 @@
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#include <soc/clock.h>
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#include <soc/pwm.h>
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#include <soc/grf.h>
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#include <soc/rk808.h>
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#include <soc/tsadc.h>
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#include <stdlib.h>
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#include <symbols.h>
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@ -38,7 +39,7 @@
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "timer.h"
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#include "board.h"
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static void regulate_vdd_log(unsigned int mv)
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{
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@ -76,6 +77,12 @@ static void configure_l2ctlr(void)
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write_l2ctlr(l2ctlr);
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}
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static void sdmmc_power_off(void)
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{
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rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
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rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
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}
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void main(void)
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{
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#if CONFIG_COLLECT_TIMESTAMPS
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@ -90,6 +97,9 @@ void main(void)
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configure_l2ctlr();
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tsadc_init();
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/* Need to power cycle SD card to ensure it is properly reset. */
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sdmmc_power_off();
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/* vdd_log 1200mv is enough for ddr run 666Mhz */
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regulate_vdd_log(1200);
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#if CONFIG_COLLECT_TIMESTAMPS
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@ -52,6 +52,7 @@ static void configure_sdmmc(void)
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/* use sdmmc0 io, disable JTAG function */
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writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
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/* Note: these power rail definitions are copied in romstage.c */
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rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
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rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
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@ -31,6 +31,7 @@
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#include <soc/clock.h>
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#include <soc/pwm.h>
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#include <soc/grf.h>
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#include <soc/rk808.h>
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#include <soc/tsadc.h>
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#include <stdlib.h>
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#include <symbols.h>
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@ -38,7 +39,7 @@
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "timer.h"
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#include "board.h"
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static void regulate_vdd_log(unsigned int mv)
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{
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@ -76,6 +77,12 @@ static void configure_l2ctlr(void)
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write_l2ctlr(l2ctlr);
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}
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static void sdmmc_power_off(void)
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{
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rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
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rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
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}
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void main(void)
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{
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#if CONFIG_COLLECT_TIMESTAMPS
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@ -90,6 +97,9 @@ void main(void)
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configure_l2ctlr();
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tsadc_init();
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/* Need to power cycle SD card to ensure it is properly reset. */
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sdmmc_power_off();
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/* vdd_log 1200mv is enough for ddr run 666Mhz */
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regulate_vdd_log(1200);
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#if CONFIG_COLLECT_TIMESTAMPS
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@ -62,6 +62,7 @@ static void configure_sdmmc(void)
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/* use sdmmc0 io, disable JTAG function */
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writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
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/* Note: these power rail definitions are copied in romstage.c */
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switch (board_id()) {
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case 0:
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rk808_configure_ldo(PMIC_BUS, 8, 3300); /* VCCIO_SD */
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@ -31,6 +31,7 @@
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#include <soc/clock.h>
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#include <soc/pwm.h>
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#include <soc/grf.h>
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#include <soc/rk808.h>
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#include <soc/tsadc.h>
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#include <stdlib.h>
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#include <symbols.h>
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@ -38,7 +39,7 @@
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "timer.h"
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#include "board.h"
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static void regulate_vdd_log(unsigned int mv)
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{
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@ -76,6 +77,20 @@ static void configure_l2ctlr(void)
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write_l2ctlr(l2ctlr);
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}
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static void sdmmc_power_off(void)
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{
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switch (board_id()) {
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case 0:
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rk808_configure_ldo(PMIC_BUS, 8, 0); /* VCCIO_SD */
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gpio_output(GPIO(7, C, 5), 0); /* SD_EN */
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break;
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default:
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rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
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rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
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break;
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}
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}
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void main(void)
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{
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#if CONFIG_COLLECT_TIMESTAMPS
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@ -90,6 +105,9 @@ void main(void)
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configure_l2ctlr();
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tsadc_init();
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/* Need to power cycle SD card to ensure it is properly reset. */
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sdmmc_power_off();
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/* vdd_log 1200mv is enough for ddr run 666Mhz */
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regulate_vdd_log(1200);
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#if CONFIG_COLLECT_TIMESTAMPS
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@ -49,6 +49,7 @@ romstage-y += gpio.c
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romstage-y += spi.c
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romstage-y += media.c
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romstage-y += sdram.c
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romstage-y += rk808.c
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romstage-y += pwm.c
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romstage-y += tsadc.c
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@ -53,6 +53,11 @@ void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts)
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{
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uint8_t vsel;
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if (!millivolts) {
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rk808_clrsetbits(bus, LDO_EN, 1 << (ldo - 1), 0);
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return;
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}
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switch (ldo) {
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case 1:
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case 2:
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