From dbfb6b92654f1fbc8799c46f142e31deea73fd9d Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 4 May 2023 23:17:44 +0200 Subject: [PATCH] soc/amd/*/acpi/northbridge,pci0: don't hide PCI0 root device from OS Return 0xf from PCI0 _STA method so that bit 2 is set which indicates that the device should be shown in the user interface. This ports commit c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS") forward from Stoneyridge to the newer AMD SoCs. TEST=On Mandolin the PCI Express Root Complex now shows up in the device manager on Windows 10 and when switching the view to 'devices by connection', all PCI(e) devices are shown below it. Signed-off-by: Felix Held Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/acpi/pci0.asl | 2 +- src/soc/amd/glinda/acpi/pci0.asl | 2 +- src/soc/amd/mendocino/acpi/pci0.asl | 2 +- src/soc/amd/phoenix/acpi/pci0.asl | 2 +- src/soc/amd/picasso/acpi/northbridge.asl | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl index 93bfb1fccd..fb02a02c3b 100644 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ b/src/soc/amd/cezanne/acpi/pci0.asl @@ -10,7 +10,7 @@ Device(PCI0) { } Method(_STA, 0, NotSerialized) { - Return(0x0B) /* Status is visible */ + Return(0x0f) /* Status is visible */ } /* Operating System Capabilities Method */ diff --git a/src/soc/amd/glinda/acpi/pci0.asl b/src/soc/amd/glinda/acpi/pci0.asl index 2f7e0baa06..925f853abd 100644 --- a/src/soc/amd/glinda/acpi/pci0.asl +++ b/src/soc/amd/glinda/acpi/pci0.asl @@ -12,7 +12,7 @@ Device(PCI0) { } Method(_STA, 0, NotSerialized) { - Return(0x0B) /* Status is visible */ + Return(0x0f) /* Status is visible */ } /* Operating System Capabilities Method */ diff --git a/src/soc/amd/mendocino/acpi/pci0.asl b/src/soc/amd/mendocino/acpi/pci0.asl index 5bf2f3e7c7..5cc6f9fb1c 100644 --- a/src/soc/amd/mendocino/acpi/pci0.asl +++ b/src/soc/amd/mendocino/acpi/pci0.asl @@ -12,7 +12,7 @@ Device(PCI0) { } Method(_STA, 0, NotSerialized) { - Return(0x0B) /* Status is visible */ + Return(0x0f) /* Status is visible */ } /* Operating System Capabilities Method */ diff --git a/src/soc/amd/phoenix/acpi/pci0.asl b/src/soc/amd/phoenix/acpi/pci0.asl index 665fe30423..345b66ea9a 100644 --- a/src/soc/amd/phoenix/acpi/pci0.asl +++ b/src/soc/amd/phoenix/acpi/pci0.asl @@ -12,7 +12,7 @@ Device(PCI0) { } Method(_STA, 0, NotSerialized) { - Return(0x0B) /* Status is visible */ + Return(0x0f) /* Status is visible */ } /* Operating System Capabilities Method */ diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 6850a1a0e4..99d04b5ba6 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -15,7 +15,7 @@ Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ Method(_STA, 0, NotSerialized) { - Return(0x0B) /* Status is visible */ + Return(0x0f) /* Status is visible */ } /* PCI Routing Table */