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drivers/intel/fsp2_0: Have provision for caching TOM region 

This patch enables early caching of TOM region to optimize the boot
time if valid mrc cache is found (i.e. except the first boot after
flashing/updating few AP firmware image).

TEST=Able to build and boot google/rex to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia575ad0f99d5b0fd015e40b0862e8560700f6c83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2023-02-28 07:01:26 +00:00 committed by Lean Sheng Tan
parent 725dd39f5b
commit dbfbfaf608
1 changed files with 10 additions and 0 deletions
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10
src/drivers/intel/fsp2_0/memory_init.c
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@ -24,6 +24,10 @@
#include <types.h>
#include <vb2_api.h>
#if CONFIG(SOC_INTEL_COMMON_BASECODE_TOM)
#include <intelbasecode/tom.h>
#endif
static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
@ -255,6 +259,12 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"FSPM_ARCH_UPD not found!\n");
/* Early caching of TOM region if valid mrc cache data is found */
#if (CONFIG(SOC_INTEL_COMMON_BASECODE_TOM))
if (arch_upd->NvsBufferPtr)
early_tom_enable_cache_range();
#endif
/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);