sb/intel/bd82x6x: Don't use device_t
Use of device_t is deprecated. Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
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}
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#ifndef __SMM__
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static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
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static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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{
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u32 dword = pci_read_config32(dev, offset);
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memcpy(ptr, &dword, sizeof(dword));
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@ -543,7 +543,7 @@ void intel_me_finalize_smm(void)
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#else /* !__SMM__ */
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/* Determine the path that we should take based on ME status */
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static me_bios_path intel_me_path(device_t dev)
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static me_bios_path intel_me_path(struct device *dev)
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{
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me_bios_path path = ME_DISABLE_BIOS_PATH;
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struct me_hfs hfs;
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@ -610,7 +610,7 @@ static me_bios_path intel_me_path(device_t dev)
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}
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/* Prepare ME for MEI messages */
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static int intel_mei_setup(device_t dev)
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static int intel_mei_setup(struct device *dev)
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{
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struct resource *res;
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struct mei_csr host;
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@ -640,7 +640,7 @@ static int intel_mei_setup(device_t dev)
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}
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/* Read the Extend register hash of ME firmware */
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static int intel_me_extend_valid(device_t dev)
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static int intel_me_extend_valid(struct device *dev)
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{
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struct me_heres status;
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u32 extend[8] = {0};
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@ -687,14 +687,14 @@ static int intel_me_extend_valid(device_t dev)
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}
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/* Hide the ME virtual PCI devices */
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static void intel_me_hide(device_t dev)
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static void intel_me_hide(struct device *dev)
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{
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dev->enabled = 0;
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pch_enable(dev);
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}
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/* Check whether ME is present and do basic init */
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static void intel_me_init(device_t dev)
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static void intel_me_init(struct device *dev)
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{
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me_bios_path path = intel_me_path(dev);
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@ -736,7 +736,7 @@ static void intel_me_init(device_t dev)
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}
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}
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static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
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}
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#ifndef __SMM__
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static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
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static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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{
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u32 dword = pci_read_config32(dev, offset);
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memcpy(ptr, &dword, sizeof(dword));
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@ -523,7 +523,7 @@ void intel_me8_finalize_smm(void)
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#else /* !__SMM__ */
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/* Determine the path that we should take based on ME status */
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static me_bios_path intel_me_path(device_t dev)
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static me_bios_path intel_me_path(struct device *dev)
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{
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me_bios_path path = ME_DISABLE_BIOS_PATH;
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struct me_hfs hfs;
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@ -597,7 +597,7 @@ static me_bios_path intel_me_path(device_t dev)
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}
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/* Prepare ME for MEI messages */
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static int intel_mei_setup(device_t dev)
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static int intel_mei_setup(struct device *dev)
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{
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struct resource *res;
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struct mei_csr host;
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@ -627,7 +627,7 @@ static int intel_mei_setup(device_t dev)
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}
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/* Read the Extend register hash of ME firmware */
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static int intel_me_extend_valid(device_t dev)
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static int intel_me_extend_valid(struct device *dev)
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{
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struct me_heres status;
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u32 extend[8] = {0};
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@ -674,14 +674,14 @@ static int intel_me_extend_valid(device_t dev)
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}
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/* Hide the ME virtual PCI devices */
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static void intel_me_hide(device_t dev)
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static void intel_me_hide(struct device *dev)
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{
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dev->enabled = 0;
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pch_enable(dev);
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}
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/* Check whether ME is present and do basic init */
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static void intel_me_init(device_t dev)
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static void intel_me_init(struct device *dev)
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{
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me_bios_path path = intel_me_path(dev);
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me_bios_payload mbp_data;
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@ -739,7 +739,7 @@ static void intel_me_init(device_t dev)
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}
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}
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static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -208,9 +208,9 @@ static void pch_hide_devfn(unsigned devfn)
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}
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/* Check if any port in set X to X+3 is enabled */
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static int pch_pcie_check_set_enabled(device_t dev)
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static int pch_pcie_check_set_enabled(struct device *dev)
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{
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device_t port;
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struct device *port;
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int port_func;
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int dev_func = PCI_FUNC(dev->path.pci.devfn);
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@ -258,7 +258,7 @@ static void pch_pcie_function_swap(u8 old_fn, u8 new_fn)
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static void pch_pcie_devicetree_update(
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struct southbridge_intel_bd82x6x_config *config)
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{
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device_t dev;
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struct device *dev;
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/*
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* hotplug map should also be updated along with their
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@ -312,7 +312,7 @@ static void pch_pcie_devicetree_update(
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}
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/* Special handling for PCIe Root Port devices */
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static void pch_pcie_enable(device_t dev)
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static void pch_pcie_enable(struct device *dev)
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{
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struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
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u32 reg32;
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@ -422,7 +422,7 @@ static void pch_pcie_enable(device_t dev)
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}
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}
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void pch_enable(device_t dev)
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void pch_enable(struct device *dev)
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{
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u32 reg32;
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@ -64,7 +64,7 @@ void intel_pch_finalize_smm(void);
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#if !defined(__PRE_RAM__)
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#if !defined(__SIMPLE_DEVICE__)
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#include "chip.h"
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void pch_enable(device_t dev);
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void pch_enable(struct device *dev);
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#endif
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int pch_silicon_revision(void);
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int pch_silicon_type(void);
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