mainboard/amd: Remove AMD Torpedo mainboard
This also permits removal of vc/amd/agesa/f12, as it was the only mainboard using it. That will in turn allow resolving some unique Coverity issues reported against that source. Change-Id: I73f570f01fcb5ba0e306508a569ea97f432596b3 Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Joe Moore
Patrick Georgi
parent
4f1d6ff42e
commit
dc0b1875a9
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@ -1,187 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <AGESA.h>
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#include <amdlib.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include "Hudson-2.h"
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#include <stdlib.h>
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#include <southbridge/amd/cimx/sb900/gpio_oem.h>
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
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{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/* Call the host environment interface to provide a user hook opportunity. */
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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UINTN FcnData;
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MEM_DATA_STRUCT *MemData;
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UINT32 AcpiMmioAddr;
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UINT32 GpioMmioAddr;
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UINT8 Data8;
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UINT16 Data16;
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FcnData = Data;
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MemData = ConfigPtr;
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Status = AGESA_SUCCESS;
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/* Get SB MMIO Base (AcpiMmioAddr) */
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WriteIo8 (0xCD6, 0x27);
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Data8 = ReadIo8(0xCD7);
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Data16 = Data8 << 8;
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WriteIo8 (0xCD6, 0x26);
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Data8 = ReadIo8(0xCD7);
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Data16 |= Data8;
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AcpiMmioAddr = (UINT32)Data16 << 16;
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GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
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switch (MemData->ParameterListPtr->DDR3Voltage) {
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case VOLT1_35:
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
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Data8 |= (UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
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break;
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case VOLT1_25:
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
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break;
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case VOLT1_5:
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default:
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
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Data8 |= (UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
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}
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return Status;
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}
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/* PCIE slot reset control */
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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UINTN FcnData;
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PCIe_SLOT_RESET_INFO *ResetInfo;
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UINT32 GpioMmioAddr;
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UINT32 AcpiMmioAddr;
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UINT8 Data8;
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UINT16 Data16;
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FcnData = Data;
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ResetInfo = ConfigPtr;
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// Get SB MMIO Base (AcpiMmioAddr)
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WriteIo8(0xCD6, 0x27);
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Data8 = ReadIo8(0xCD7);
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Data16 = Data8 << 8;
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WriteIo8(0xCD6, 0x26);
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Data8 = ReadIo8(0xCD7);
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Data16 |= Data8;
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AcpiMmioAddr = (UINT32)Data16 << 16;
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Status = AGESA_UNSUPPORTED;
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GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
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if (ResetInfo->ResetControl == DeassertSlotReset) {
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if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert
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// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
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if (Data8 & BIT7) {
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
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while (!(Data8 & BIT7)) {
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
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}
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// GPIO44: PE_GPIO0 MXM Reset
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
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Data8 |= BIT6 ;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
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Status = AGESA_SUCCESS;
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}
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} else {
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Status = AGESA_UNSUPPORTED;
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}
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// Travis
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
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//DE-Assert ALL PCIE RESET
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// APU GPP0 (Dev 4)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
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// APU GPP1 (Dev 5)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
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// APU GPP2 (Dev 6)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
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// APU GPP3 (Dev 7)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
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} else {
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if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported
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// GPIO44: PE_GPIO0 MXM Reset
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
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Status = AGESA_SUCCESS;
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}
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// Travis
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
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//Assert ALL PCIE RESET
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// APU GPP0 (Dev 4)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
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// APU GPP1 (Dev 5)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
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// APU GPP2 (Dev 6)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
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// APU GPP3 (Dev 7)
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
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}
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return Status;
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}
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@ -1,137 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_AMD_TORPEDO
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_AMD_AGESA_FAMILY12
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select NORTHBRIDGE_AMD_AGESA_FAMILY12
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select SOUTHBRIDGE_AMD_CIMX_SB900
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select SUPERIO_SMSC_KBC1100
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_2048
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select GFXUMA
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config MAINBOARD_DIR
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string
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default amd/torpedo
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config MAINBOARD_PART_NUMBER
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string
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default "Torpedo"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config MAX_CPUS
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int
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default 4
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config VGA_BIOS
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bool
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default n
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#config VGA_BIOS_FILE
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# string "VGA BIOS path and filename"
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# depends on VGA_BIOS
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# default "rom/video/LlanoGenericVbios.bin"
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config VGA_BIOS_ID
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string "VGA device PCI IDs"
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depends on VGA_BIOS
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default "1002,9641"
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config AHCI_BIOS
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bool
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default n
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#config AHCI_BIOS_FILE
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# string "AHCI ROM path and filename"
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# depends on AHCI_BIOS
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# default "rom/ahci/sb900.bin"
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config AHCI_BIOS_ID
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string "AHCI device PCI IDs"
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depends on AHCI_BIOS
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default "1022,7801"
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config XHC_BIOS
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bool
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default n
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#config XHC_BIOS_FILE
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# string "XHC BIOS path and filename"
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# depends on XHC_BIOS
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# default "rom/xhc/Xhc.rom"
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config XHC_BIOS_ID
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string "XHC device PCI IDs"
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depends on XHC_BIOS
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default "1022,7812"
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config SATA_CONTROLLER_MODE
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hex
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default 0x0
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config ONBOARD_LAN
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bool
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default y
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config ONBOARD_1394
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bool
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default y
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config ONBOARD_USB30
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bool
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default n
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config ONBOARD_BLUETOOTH
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bool
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default y
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config ONBOARD_WEBCAM
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bool
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default y
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config ONBOARD_TRAVIS
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bool
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default y
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config ONBOARD_LIGHTSENSOR
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bool
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default n
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endif # BOARD_AMD_TORPEDO
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@ -1,2 +0,0 @@
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config BOARD_AMD_TORPEDO
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bool "Torpedo"
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@ -1,37 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ifeq ($(CONFIG_AHCI_BIOS),y)
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stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
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cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
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pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
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pci$(stripped_ahcibios_id).rom-type := optionrom
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endif
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ifeq ($(CONFIG_XHC_BIOS),y)
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stripped_xhcbios_id = $(call strip_quotes,$(CONFIG_XHC_BIOS_ID))
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cbfs-files-$(CONFIG_XHC_BIOS) += pci$(stripped_xhcbios_id).rom
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pci$(stripped_xhcbios_id).rom-file := $(call strip_quotes,$(CONFIG_XHC_BIOS_FILE))
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pci$(stripped_xhcbios_id).rom-type := optionrom
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endif
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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romstage-y += gpio.c
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ramstage-y += buildOpts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += OemCustomize.c
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@ -1,217 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
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#ifndef BIOS_SIZE
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#define BIOS_SIZE 0x04 //04 - 1MB
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#endif
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#define LEGACY_FREE 0x00
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#if !CONFIG(ONBOARD_USB30)
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#define XHCI_SUPPORT 0x01
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#endif
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//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot.
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//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
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/**
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* Module Specific Defines for platform BIOS
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*
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*/
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/**
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* PCIEX_BASE_ADDRESS - Define PCIE base address
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*/
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#ifdef MOVE_PCIEBAR_TO_F0000000
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#define PCIEX_BASE_ADDRESS 0xF7000000
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#else
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#define PCIEX_BASE_ADDRESS 0xE0000000
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#endif
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||||
/**
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* SMBUS0_BASE_ADDRESS - Smbus base address
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||||
*
|
||||
*/
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||||
#ifndef SMBUS0_BASE_ADDRESS
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#define SMBUS0_BASE_ADDRESS 0xB00
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#endif
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||||
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||||
/**
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||||
* SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
|
||||
*
|
||||
*/
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||||
#ifndef SMBUS1_BASE_ADDRESS
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#define SMBUS1_BASE_ADDRESS 0xB20
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#endif
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||||
|
||||
/**
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* SIO_PME_BASE_ADDRESS - Super IO PME base address
|
||||
*
|
||||
*/
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||||
#ifndef SIO_PME_BASE_ADDRESS
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#define SIO_PME_BASE_ADDRESS 0xE00
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#endif
|
||||
|
||||
/**
|
||||
* SPI_BASE_ADDRESS - SPI controller (ROM) base address
|
||||
*
|
||||
*/
|
||||
#ifndef SPI_BASE_ADDRESS
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||||
#define SPI_BASE_ADDRESS 0xFEC10000
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||||
#endif
|
||||
|
||||
/**
|
||||
* WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
|
||||
*
|
||||
*/
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||||
#ifndef WATCHDOG_TIMER_BASE_ADDRESS
|
||||
#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
|
||||
#endif
|
||||
|
||||
/**
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||||
* HPET_BASE_ADDRESS - HPET base address
|
||||
*
|
||||
*/
|
||||
#ifndef HPET_BASE_ADDRESS
|
||||
#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
|
||||
#endif
|
||||
|
||||
/**
|
||||
* ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
|
||||
*
|
||||
*/
|
||||
#ifdef ALT_ADDR_400
|
||||
#define ACPI_BLK_BASE 0x400
|
||||
#else
|
||||
#define ACPI_BLK_BASE 0x800
|
||||
#endif
|
||||
|
||||
#define PM1_STATUS_OFFSET 0x00
|
||||
#define PM1_ENABLE_OFFSET 0x02
|
||||
#define PM1_CONTROL_OFFSET 0x04
|
||||
#define PM_TIMER_OFFSET 0x08
|
||||
#define CPU_CONTROL_OFFSET 0x10
|
||||
#define EVENT_STATUS_OFFSET 0x20
|
||||
#define EVENT_ENABLE_OFFSET 0x24
|
||||
|
||||
/**
|
||||
* PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
|
||||
*
|
||||
*/
|
||||
#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
|
||||
|
||||
/**
|
||||
* PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
|
||||
*
|
||||
*/
|
||||
#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
|
||||
|
||||
/**
|
||||
* PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
|
||||
*
|
||||
*/
|
||||
#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
|
||||
|
||||
/**
|
||||
* CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
|
||||
*
|
||||
*/
|
||||
#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
|
||||
|
||||
/**
|
||||
* GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
|
||||
*
|
||||
*/
|
||||
#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
|
||||
|
||||
/**
|
||||
* SMI_CMD_PORT - ACPI SMI Command block base address
|
||||
*
|
||||
*/
|
||||
#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
|
||||
|
||||
/**
|
||||
* ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
|
||||
*
|
||||
*/
|
||||
#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
|
||||
|
||||
/**
|
||||
* SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
|
||||
* Define value for SSID while SATA controller set to IDE mode.
|
||||
*/
|
||||
#define SATA_IDE_MODE_SSID 0x78001022
|
||||
/**
|
||||
* SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
|
||||
* Define value for SSID while SATA controller set to RAID mode.
|
||||
*/
|
||||
#define SATA_RAID_MODE_SSID 0x78021022
|
||||
|
||||
/**
|
||||
* SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
|
||||
* Define value for SSID while SATA controller set to RAID5 mode.
|
||||
*/
|
||||
#define SATA_RAID5_MODE_SSID 0x78031022
|
||||
|
||||
/**
|
||||
* SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
|
||||
* Define value for SSID while SATA controller set to AHCI mode.
|
||||
*/
|
||||
#define SATA_AHCI_SSID 0x78011022
|
||||
|
||||
/**
|
||||
* OHCI_SSID - All SB OHCI controllers SSID value.
|
||||
*
|
||||
*/
|
||||
#define OHCI_SSID 0x78071022
|
||||
|
||||
/**
|
||||
* EHCI_SSID - All SB EHCI controllers SSID value.
|
||||
*
|
||||
*/
|
||||
#define EHCI_SSID 0x78081022
|
||||
|
||||
/**
|
||||
* OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
|
||||
*
|
||||
*/
|
||||
#define OHCI4_SSID 0x78091022
|
||||
|
||||
/**
|
||||
* SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
|
||||
*
|
||||
*/
|
||||
#define SMBUS_SSID 0x780B1022
|
||||
|
||||
/**
|
||||
* IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
|
||||
*
|
||||
*/
|
||||
#define IDE_SSID 0x780C1022
|
||||
|
||||
/**
|
||||
* AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
|
||||
*
|
||||
*/
|
||||
#define AZALIA_SSID 0x780D1022
|
||||
|
||||
/**
|
||||
* LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
|
||||
*
|
||||
*/
|
||||
#define LPC_SSID 0x780E1022
|
||||
|
||||
/**
|
||||
* PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
|
||||
*
|
||||
*/
|
||||
#define PCIB_SSID 0x780F1022
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
#include <PlatformMemoryConfiguration.h>
|
||||
|
||||
static const PCIe_PORT_DESCRIPTOR PortList[] = {
|
||||
// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
|
||||
PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, BIT2)
|
||||
},
|
||||
// Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 19),
|
||||
PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, BIT3)
|
||||
},
|
||||
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
|
||||
PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0)
|
||||
},
|
||||
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
|
||||
PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0)
|
||||
},
|
||||
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
|
||||
PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0)
|
||||
},
|
||||
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
|
||||
PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0)
|
||||
}
|
||||
};
|
||||
|
||||
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
|
||||
// Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
|
||||
},
|
||||
// Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
|
||||
}
|
||||
};
|
||||
|
||||
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
|
||||
.Flags = DESCRIPTOR_TERMINATE_LIST,
|
||||
.SocketId = 0,
|
||||
.PciePortList = PortList,
|
||||
.DdiLinkList = DdiList,
|
||||
};
|
||||
|
||||
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
|
||||
{
|
||||
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
|
||||
InitEarly->GnbConfig.PsppPolicy = 0;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CUSTOMER OVERIDES MEMORY TABLE
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
|
||||
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
|
||||
PSO_END
|
||||
};
|
||||
|
||||
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
|
||||
{
|
||||
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
|
||||
}
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* IDS Option File
|
||||
*
|
||||
* This file is used to switch on/off IDS features.
|
||||
*
|
||||
*/
|
||||
#ifndef _OPTION_IDS_H_
|
||||
#define _OPTION_IDS_H_
|
||||
|
||||
/**
|
||||
*
|
||||
* This file generates the defaults tables for the Integrated Debug Support
|
||||
* Module. The documented build options are imported from a user controlled
|
||||
* file for processing. The build options for the Integrated Debug Support
|
||||
* Module are listed below:
|
||||
*
|
||||
* IDSOPT_IDS_ENABLED
|
||||
* IDSOPT_ERROR_TRAP_ENABLED
|
||||
* IDSOPT_CONTROL_ENABLED
|
||||
* IDSOPT_TRACING_ENABLED
|
||||
* IDSOPT_PERF_ANALYSIS
|
||||
* IDSOPT_ASSERT_ENABLED
|
||||
* IDS_DEBUG_PORT
|
||||
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
|
||||
*
|
||||
**/
|
||||
|
||||
//#define IDSOPT_IDS_ENABLED TRUE
|
||||
//#define IDSOPT_TRACING_ENABLED TRUE
|
||||
#define IDSOPT_ASSERT_ENABLED TRUE
|
||||
|
||||
//#define IDSOPT_DEBUG_ENABLED FALSE
|
||||
//#undef IDSOPT_HOST_SIMNOW
|
||||
//#define IDSOPT_HOST_SIMNOW FALSE
|
||||
//#undef IDSOPT_HOST_HDT
|
||||
//#define IDSOPT_HOST_HDT FALSE
|
||||
//#define IDS_DEBUG_PORT 0x80
|
||||
|
||||
#endif
|
||||
|
|
@ -1,240 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0, Serialized)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, Serialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF, 0, Serialized) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF, 0, Serialized) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
|
|
@ -1,308 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, INTC, 0 },
|
||||
Package(){0x0001FFFF, 1, INTD, 0 },
|
||||
/* Bus 0, Dev 2 - */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - */
|
||||
Package(){0x0003FFFF, 0, INTD, 0 },
|
||||
Package(){0x0003FFFF, 1, INTA, 0 },
|
||||
Package(){0x0003FFFF, 2, INTB, 0 },
|
||||
Package(){0x0003FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
Package(){0x0005FFFF, 0, INTB, 0 },
|
||||
Package(){0x0005FFFF, 1, INTC, 0 },
|
||||
Package(){0x0005FFFF, 2, INTD, 0 },
|
||||
Package(){0x0005FFFF, 3, INTA, 0 },
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
Package(){0x0010FFFF, 0, INTC, 0 },
|
||||
Package(){0x0010FFFF, 1, INTB, 0 },
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0015FFFF, 0, INTA, 0 },
|
||||
Package(){0x0015FFFF, 1, INTB, 0 },
|
||||
Package(){0x0015FFFF, 2, INTC, 0 },
|
||||
Package(){0x0015FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, 0, 18 },
|
||||
Package(){0x0001FFFF, 1, 0, 19 },
|
||||
/* Bus 0, Dev 2 */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
Package(){0x0002FFFF, 1, 0, 19 },
|
||||
Package(){0x0002FFFF, 2, 0, 16 },
|
||||
Package(){0x0002FFFF, 3, 0, 17 },
|
||||
/* Bus 0, Dev 3 */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
Package(){0x0003FFFF, 1, 0, 16 },
|
||||
Package(){0x0003FFFF, 2, 0, 17 },
|
||||
Package(){0x0003FFFF, 3, 0, 18 },
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
Package(){0x0004FFFF, 1, 0, 17 },
|
||||
Package(){0x0004FFFF, 2, 0, 18 },
|
||||
Package(){0x0004FFFF, 3, 0, 19 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
Package(){0x0005FFFF, 0, 0, 17 },
|
||||
Package(){0x0005FFFF, 1, 0, 18 },
|
||||
Package(){0x0005FFFF, 2, 0, 19 },
|
||||
Package(){0x0005FFFF, 3, 0, 16 },
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
Package(){0x0006FFFF, 0, 0, 18 },
|
||||
Package(){0x0006FFFF, 1, 0, 19 },
|
||||
Package(){0x0006FFFF, 2, 0, 16 },
|
||||
Package(){0x0006FFFF, 3, 0, 17 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
Package(){0x0007FFFF, 0, 0, 19 },
|
||||
Package(){0x0007FFFF, 1, 0, 16 },
|
||||
Package(){0x0007FFFF, 2, 0, 17 },
|
||||
Package(){0x0007FFFF, 3, 0, 18 },
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
Package(){0x0010FFFF, 0, 0, 18 },
|
||||
Package(){0x0010FFFF, 1, 0, 17 },
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0015FFFF, 0, 0, 16 },
|
||||
Package(){0x0015FFFF, 1, 0, 17 },
|
||||
Package(){0x0015FFFF, 2, 0, 18 },
|
||||
Package(){0x0015FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* For Device(PBR2) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* For Device(PBR2) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS3, Package(){
|
||||
/* For Device(PBR3) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS3, Package(){
|
||||
/* For Device(PBR3) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* For Device(PBR4) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* For Device(PBR4) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* For Device(PBR5) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* For Device(PBR5) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* For Device(PBR6) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* For Device(PBR6) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* For Device(PBR7) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* For Device(PBR7) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PE0, Package(){
|
||||
/* For Device(PE20) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APE0, Package(){
|
||||
/* For Device(PE20) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PE1, Package(){
|
||||
/* For Device(PE21) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APE1, Package(){
|
||||
/* For Device(PE21) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PE2, Package(){
|
||||
/* For Device(PE22) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APE2, Package(){
|
||||
/* For Device(PE22) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE3, Package(){
|
||||
/* For Device(PE23) PIC mode*/
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APE3, Package(){
|
||||
/* For Device(PE23) APIC mode*/
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
}
|
||||
|
|
@ -1,145 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
|
||||
extern u32 apicid_sb900;
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3);
|
||||
|
||||
/* Write SB900 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 2, 5, 1);
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 3, 5, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
|
@ -1 +0,0 @@
|
|||
Category: eval
|
||||
|
|
@ -1,221 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD User options selection for a Sabine/Lynx platform solution system
|
||||
*
|
||||
* This file is placed in the user's platform directory and contains the
|
||||
* build option selections desired for that platform.
|
||||
*
|
||||
* For Information about this file, see @ref platforminstall.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <AGESA.h>
|
||||
|
||||
|
||||
/* Select the CPU family. */
|
||||
#define INSTALL_FAMILY_10_SUPPORT FALSE
|
||||
#define INSTALL_FAMILY_12_SUPPORT TRUE
|
||||
#define INSTALL_FAMILY_14_SUPPORT FALSE
|
||||
#define INSTALL_FAMILY_15_SUPPORT FALSE
|
||||
|
||||
/* Select the CPU socket type. */
|
||||
#define INSTALL_G34_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_C32_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_FS1_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_FM1_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_FP1_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_FT1_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
|
||||
|
||||
/*
|
||||
* Agesa optional capabilities selection.
|
||||
* Uncomment and mark FALSE those features you wish to include in the build.
|
||||
* Comment out or mark TRUE those features you want to REMOVE from the build.
|
||||
*/
|
||||
|
||||
#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_RDIMMS_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
|
||||
#define BLDOPT_REMOVE_DCT_INTERLEAVE FALSE
|
||||
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
|
||||
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
|
||||
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_DDR2_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_DDR3_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
|
||||
#define BLDOPT_REMOVE_SRAT TRUE
|
||||
#define BLDOPT_REMOVE_SLIT TRUE
|
||||
#define BLDOPT_REMOVE_WHEA TRUE
|
||||
#define BLDOPT_REMOVE_DMI FALSE
|
||||
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
|
||||
|
||||
//For revision C single-link processors
|
||||
#define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Define the RELEASE VERSION string
|
||||
*
|
||||
* The Release Version string should identify the next planned release.
|
||||
* When a branch is made in preparation for a release, the release manager
|
||||
* should change/confirm that the branch version of this file contains the
|
||||
* string matching the desired version for the release. The trunk version of
|
||||
* the file should always contain a trailing 'X'. This will make sure that a
|
||||
* development build from trunk will not be confused for a released version.
|
||||
* The release manager will need to remove the trailing 'X' and update the
|
||||
* version string as appropriate for the release. The trunk copy of this file
|
||||
* should also be updated/incremented for the next expected version, + trailing 'X'
|
||||
****************************************************************************/
|
||||
// This is the delivery package title, "LlanoPI "
|
||||
// This string MUST be exactly 8 characters long
|
||||
#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
|
||||
|
||||
// This is the release version number of the AGESA component
|
||||
// This string MUST be exactly 12 characters long
|
||||
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
|
||||
|
||||
/* The following definitions specify the default values for various parameters
|
||||
* in which there are no clearly defined defaults to be used in the common file.
|
||||
* The values below are based on product and BKDG content, please consult the
|
||||
* AGESA Memory team for consultation.
|
||||
*/
|
||||
#define DFLT_SCRUB_DRAM_RATE (0)
|
||||
#define DFLT_SCRUB_L2_RATE (0)
|
||||
#define DFLT_SCRUB_L3_RATE (0)
|
||||
#define DFLT_SCRUB_IC_RATE (0)
|
||||
#define DFLT_SCRUB_DC_RATE (0)
|
||||
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define DFLT_VRM_SLEW_RATE (5000)
|
||||
|
||||
/* Build configuration values here.
|
||||
*/
|
||||
#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000
|
||||
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0
|
||||
#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
|
||||
#define BLDCFG_PLAT_NUM_IO_APICS 3
|
||||
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
|
||||
#define BLDCFG_MEM_INIT_PSTATE 0
|
||||
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
|
||||
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY
|
||||
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
|
||||
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
|
||||
#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
|
||||
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
|
||||
#define BLDCFG_MEMORY_POWER_DOWN TRUE
|
||||
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
|
||||
#define BLDCFG_ONLINE_SPARE FALSE
|
||||
#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
|
||||
#define BLDCFG_BANK_SWIZZLE TRUE
|
||||
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
|
||||
#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
|
||||
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
|
||||
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
|
||||
#define BLDCFG_USE_BURST_MODE FALSE
|
||||
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
|
||||
#define BLDCFG_ENABLE_ECC_FEATURE TRUE
|
||||
#define BLDCFG_ECC_REDIRECTION FALSE
|
||||
#define BLDCFG_SCRUB_DRAM_RATE 0
|
||||
#define BLDCFG_SCRUB_L2_RATE 0
|
||||
#define BLDCFG_SCRUB_L3_RATE 0
|
||||
#define BLDCFG_SCRUB_IC_RATE 0
|
||||
#define BLDCFG_SCRUB_DC_RATE 0
|
||||
#define BLDCFG_ECC_SYNC_FLOOD FALSE
|
||||
#define BLDCFG_ECC_SYMBOL_SIZE 4
|
||||
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
|
||||
#define BLDCFG_1GB_ALIGN FALSE
|
||||
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
|
||||
//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
|
||||
//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
|
||||
|
||||
//enable HW C1E
|
||||
#define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware
|
||||
//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415
|
||||
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6
|
||||
//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
|
||||
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
|
||||
|
||||
|
||||
//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
|
||||
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero.
|
||||
//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero.
|
||||
//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario
|
||||
//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario
|
||||
//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
|
||||
|
||||
#define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE
|
||||
#define BLDCFG_STEREO_3D_PINOUT TRUE
|
||||
|
||||
/* Process the options...
|
||||
* This file include MUST occur AFTER the user option selection settings
|
||||
*/
|
||||
CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
|
||||
{
|
||||
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull },
|
||||
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull },
|
||||
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull },
|
||||
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull },
|
||||
{ CPU_LIST_TERMINAL }
|
||||
};
|
||||
|
||||
#define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList
|
||||
//#define OPTION_NB_LCLK_DPM_INIT FALSE
|
||||
//#define OPTION_POWER_GATE FALSE
|
||||
//#define OPTION_PCIE_POWER_GATE FALSE
|
||||
//#define OPTION_ALIB FALSE
|
||||
//#define OPTION_PCIe_MID_INIT FALSE
|
||||
//#define OPTION_NB_MID_INIT FALSE
|
||||
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "heapManager.h"
|
||||
#include "CreateStruct.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Table.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "GnbInterface.h"
|
||||
#include <PlatformInstall.h>
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
#*****************************************************************************
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
chip northbridge/amd/agesa/family12/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family12
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1705 inherit
|
||||
chip northbridge/amd/agesa/family12 # CPU side of HT root complex
|
||||
chip northbridge/amd/agesa/family12 # PCI side of HT root complex
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics Bridge
|
||||
device pci 1.1 on end # Audio Controller
|
||||
device pci 2.0 on end # Root Port
|
||||
device pci 3.0 on end # Root Port
|
||||
device pci 4.0 on end # PCIE P2P bridge
|
||||
device pci 5.0 on end # PCIE P2P bridge
|
||||
device pci 6.0 on end # PCIE P2P bridge
|
||||
device pci 7.0 on end # PCIE P2P bridge
|
||||
device pci 8.0 on end # NB/SB Link P2P bridge
|
||||
end # agesa northbridge
|
||||
chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 10.0 on end # USB XHCI
|
||||
device pci 10.1 on end # USB XHCI
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE
|
||||
device pci 14.2 on end # HDA
|
||||
device pci 14.3 on # LPC
|
||||
chip superio/smsc/kbc1100
|
||||
device pnp 2e.7 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
end # kbc1100
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCI bridge
|
||||
device pci 14.5 on end # USB 2
|
||||
device pci 14.6 on end # Ethernet Controller
|
||||
device pci 14.7 on end # SD Flash Controller
|
||||
device pci 15.0 on end # PCIe PortA
|
||||
device pci 15.1 on end # PCIe PortB
|
||||
device pci 15.2 on end # PCIe PortC
|
||||
device pci 15.3 on end # PCIe PortD
|
||||
register "gpp_configuration" = "4" #1:1:1:1
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/cimx/sb900
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
device pci 18.6 on end
|
||||
device pci 18.7 on end
|
||||
end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
|
||||
end #domain
|
||||
end #northbridge/amd/agesa/family12/root_complex
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,213 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* ACPI - create the Fixed ACPI Description Tables (FADT)
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <southbridge/amd/cimx/sb900/SbPlatform.h>
|
||||
#include <version.h>
|
||||
|
||||
/*extern*/ u16 pm_base = 0x800;
|
||||
/* pm_base should be set in sb ACPI */
|
||||
/* pm_base should be got from bar2 of sb900. Here I compact ACPI
|
||||
* registers into 32 bytes limit.
|
||||
* */
|
||||
|
||||
#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
|
||||
#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
|
||||
#define ACPI_PM2_CNT_BLK (pm_base + 0x0F) /* 1 byte */
|
||||
#define ACPI_PM_TMR_BLK (pm_base + 0x08) /* 4 bytes */
|
||||
#define ACPI_GPE0_BLK (pm_base + 0x20) /* 8 bytes */
|
||||
#define ACPI_CPU_CONTORL (pm_base + 0x10) /* 6 bytes */
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
u16 val = 0;
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
pm_base &= 0xFFFF;
|
||||
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
|
||||
|
||||
/* Prepare the header */
|
||||
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = ACPI_FADT_REV_ACPI_1_0;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = asl_revision;
|
||||
|
||||
if ((uintptr_t)facs > 0xffffffff)
|
||||
printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n");
|
||||
else
|
||||
fadt->firmware_ctrl = (uintptr_t)facs;
|
||||
|
||||
if ((uintptr_t)dsdt > 0xffffffff)
|
||||
printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n");
|
||||
else
|
||||
fadt->dsdt = (uintptr_t)dsdt;
|
||||
|
||||
/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
|
||||
fadt->preferred_pm_profile = 0x03;
|
||||
fadt->sci_int = 9;
|
||||
/* disable system management mode by setting to 0: */
|
||||
fadt->smi_cmd = 0;
|
||||
fadt->acpi_enable = 0xf0;
|
||||
fadt->acpi_disable = 0xf1;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0xe2;
|
||||
|
||||
val = PM1_EVT_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
|
||||
val = PM1_CNT_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
|
||||
val = PM1_TMR_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
|
||||
val = GPE0_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
|
||||
|
||||
/* CpuControl is in \_PR.CP00, 6 bytes */
|
||||
val = CPU_CNT_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
|
||||
val = 0;
|
||||
WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
|
||||
|
||||
val = ACPI_PM2_CNT_BLK;
|
||||
WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val);
|
||||
|
||||
/* AcpiDecodeEnable, When set, SB uses the contents of the
|
||||
* PM registers at index 60-6B to decode ACPI I/O address.
|
||||
* AcpiSmiEn & SmiCmdEn */
|
||||
val = BIT0 | BIT1 | BIT2 | BIT4;
|
||||
WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
|
||||
|
||||
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
|
||||
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
|
||||
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
|
||||
fadt->pm1b_evt_blk = 0x0000;
|
||||
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
|
||||
fadt->pm1b_cnt_blk = 0x0000;
|
||||
fadt->pm2_cnt_blk = ACPI_PM2_CNT_BLK;
|
||||
fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
|
||||
fadt->gpe0_blk = ACPI_GPE0_BLK;
|
||||
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 8;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
|
||||
fadt->cst_cnt = 0xe3;
|
||||
fadt->p_lvl2_lat = 101;
|
||||
fadt->p_lvl3_lat = 1001;
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 3;
|
||||
fadt->day_alrm = 0; /* 0x7d these have to be */
|
||||
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
|
||||
fadt->century = 0; /* 0x7f to make rtc alrm work */
|
||||
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
|
||||
fadt->flags = 0x0001c1a5;/* 0x25; */
|
||||
|
||||
fadt->res2 = 0;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.access_size = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
|
||||
fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32;
|
||||
fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
|
||||
fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.access_size = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.access_size = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.access_size = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.access_size = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.access_size = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = ACPI_PM2_CNT_BLK;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.access_size = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 32;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.access_size = 0;
|
||||
fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.access_size = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
|
||||
|
||||
}
|
||||
|
|
@ -1,441 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/amd/cimx/sb900/SbPlatform.h>
|
||||
#include "gpio.h"
|
||||
#include <vendorcode/amd/cimx/sb900/AmdSbLib.h>
|
||||
|
||||
|
||||
#ifndef SB_GPIO_REG01
|
||||
#define SB_GPIO_REG01 1
|
||||
#endif
|
||||
|
||||
#ifndef SB_GPIO_REG07
|
||||
#define SB_GPIO_REG07 7
|
||||
#endif
|
||||
|
||||
#ifndef SB_GPIO_REG25
|
||||
#define SB_GPIO_REG25 25
|
||||
#endif
|
||||
|
||||
#ifndef SB_GPIO_REG26
|
||||
#define SB_GPIO_REG26 26
|
||||
#endif
|
||||
|
||||
#ifndef SB_GPIO_REG27
|
||||
#define SB_GPIO_REG27 27
|
||||
#endif
|
||||
|
||||
void gpioEarlyInit(void) {
|
||||
u8 Flags;
|
||||
u8 Data8 = 0;
|
||||
u8 StripInfo = 0;
|
||||
u8 BoardType = 1;
|
||||
u8 RegIndex8 = 0;
|
||||
u8 boardRevC = 0x2;
|
||||
u16 Data16 = 0;
|
||||
u32 Index = 0;
|
||||
u32 AcpiMmioAddr = 0;
|
||||
u32 GpioMmioAddr = 0;
|
||||
u32 IoMuxMmioAddr = 0;
|
||||
u32 MiscMmioAddr = 0;
|
||||
u32 SmiMmioAddr = 0;
|
||||
u32 andMask32 = 0;
|
||||
|
||||
// Enable HUDSON MMIO Base (AcpiMmioAddr)
|
||||
ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
|
||||
Data8 |= BIT0;
|
||||
WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
|
||||
// Get HUDSON MMIO Base (AcpiMmioAddr)
|
||||
ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
|
||||
Data16 = Data8 << 8;
|
||||
ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
|
||||
Data16 |= Data8;
|
||||
AcpiMmioAddr = (u32)Data16 << 16;
|
||||
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
|
||||
IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
|
||||
MiscMmioAddr = AcpiMmioAddr + MISC_BASE;
|
||||
Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
|
||||
if ((Data8 & BIT4) == 0) {
|
||||
BoardType = 0; // external clock board
|
||||
}
|
||||
Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
|
||||
StripInfo = (Data8 & BIT7) >> 7;
|
||||
Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
|
||||
StripInfo |= (Data8 & BIT7) >> 6;
|
||||
if (StripInfo < boardRevC) { // for old board. Rev B
|
||||
Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
|
||||
Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
|
||||
}
|
||||
for (Index = 0; Index < MAX_GPIO_NO; Index++) {
|
||||
if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
|
||||
if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
|
||||
// Configure multi-function
|
||||
Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
|
||||
}
|
||||
// Configure GPIO
|
||||
if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
|
||||
Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
|
||||
Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
|
||||
}
|
||||
if (Index == GPIO_65) {
|
||||
if (BoardType == 0) {
|
||||
Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
|
||||
}
|
||||
}
|
||||
}
|
||||
// Configure GEVENT
|
||||
if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
|
||||
SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
|
||||
|
||||
andMask32 = ~(1 << (Index - GEVENT_00));
|
||||
|
||||
//EventEnable: 0-Disable, 1-Enable
|
||||
Mmio32_And_Or(SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
|
||||
|
||||
//SciTrig: 0-Falling Edge, 1-Rising Edge
|
||||
Mmio32_And_Or(SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
|
||||
|
||||
//SciLevl: 0-Edge trigger, 1-Level Trigger
|
||||
Mmio32_And_Or(SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
|
||||
|
||||
//SmiSciEn: 0-Not send SMI, 1-Send SMI
|
||||
Mmio32_And_Or(SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
|
||||
|
||||
//SciS0En: 0-Disable, 1-Enable
|
||||
Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
|
||||
|
||||
//SciMap: 00000b ~ 11111b
|
||||
RegIndex8 = (u8)((Index - GEVENT_00) >> 2);
|
||||
Data8 = (u8)(((Index - GEVENT_00) & 0x3) * 8);
|
||||
Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
|
||||
|
||||
//SmiTrig: 0-Active Low, 1-Active High
|
||||
Mmio32_And_Or(SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
|
||||
|
||||
//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
|
||||
RegIndex8 = (u8)((Index - GEVENT_00) >> 4);
|
||||
Data8 = (u8)(((Index - GEVENT_00) & 0xF) * 2);
|
||||
Mmio32_And_Or(SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// config MXM
|
||||
// GPIO9: Input for MXM_PRESENT2#
|
||||
// GPIO10: Input for MXM_PRESENT1#
|
||||
// GPIO28: Input for MXM_PWRGD
|
||||
// GPIO35: Output for MXM Reset
|
||||
// GPIO45: Output for MXM Power Enable, active HIGH
|
||||
// GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
|
||||
// GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
|
||||
//
|
||||
// set INTE#/GPIO32 as GPO for PCIE_SW
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
|
||||
|
||||
// set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO
|
||||
|
||||
// set AD9/GPIO9 as GPI for MXM_PRESENT2#
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI
|
||||
|
||||
// set AD10/GPIO10 as GPI for MXM_PRESENT1#
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI
|
||||
|
||||
// set GNT1#/GPIO44 as GPO for MXM Reset
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO
|
||||
|
||||
// set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO
|
||||
|
||||
// set AD28/GPIO28 as GPI for MXM_PWRGD
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
|
||||
|
||||
// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
|
||||
|
||||
//
|
||||
// [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
|
||||
//
|
||||
//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
|
||||
//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
|
||||
|
||||
// check if there any GFX card
|
||||
Flags = 0;
|
||||
// Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
|
||||
// Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
|
||||
ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
|
||||
if (!(Data8 & BIT7))
|
||||
{
|
||||
//Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
|
||||
ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
|
||||
if (!(Data8 & BIT7))
|
||||
{
|
||||
Flags = 1;
|
||||
}
|
||||
}
|
||||
if (Flags)
|
||||
{
|
||||
// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
|
||||
|
||||
// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
|
||||
|
||||
//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
|
||||
SbStall (10000);
|
||||
|
||||
// Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
|
||||
|
||||
//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
|
||||
// WAIT POWER READY: GPIO28 (MXM_PWRGD)
|
||||
//while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
|
||||
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
|
||||
while (!(Data8 & BIT7))
|
||||
{
|
||||
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
|
||||
}
|
||||
// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
|
||||
//RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
|
||||
}
|
||||
else
|
||||
{
|
||||
// Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
|
||||
|
||||
//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
|
||||
SbStall (10000);
|
||||
|
||||
// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
|
||||
}
|
||||
|
||||
//
|
||||
// APU GPP0: On board LAN
|
||||
// GPIO25: PCIE_RST#_LAN, LOW active
|
||||
// GPIO63: LAN_CLKREQ#
|
||||
// GPIO197: LOM_POWER, HIGH Active
|
||||
// Clock: GPP_CLK3
|
||||
//
|
||||
// Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
|
||||
// set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3#
|
||||
RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3
|
||||
|
||||
//
|
||||
// APU GPP1: WUSB
|
||||
// GPIO1: MPCIE_RST2#, LOW active
|
||||
// GPIO13: WU_DISABLE#, LOW active
|
||||
// GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
|
||||
//
|
||||
// Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
// Setup AD01/GPIO01 as GPO for MPCIE_RST2#
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
// Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
|
||||
// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
//
|
||||
// APU GPP2: WWAN
|
||||
// GPIO0: MPCIE_RST1#, LOW active
|
||||
// GPIO14: WP_DISABLE#, LOW active
|
||||
// GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
|
||||
//
|
||||
// Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
// Set AD00/GPIO00 as GPO for MPCIE_RST1#
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
// Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
|
||||
// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
|
||||
|
||||
//
|
||||
// APU GPP3: 1394
|
||||
// GPIO59: Power control, HIGH active
|
||||
// GPIO27: PCIE_RST#_1394, LOW active
|
||||
// GPIO41: CLKREQ#
|
||||
// Clock: GPP_CLK8
|
||||
//
|
||||
// Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
// Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
|
||||
// set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2#
|
||||
|
||||
// set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
|
||||
RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
|
||||
// To fix glitch issue
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
|
||||
//
|
||||
// Enable/Disable OnBoard LAN
|
||||
//
|
||||
if (!CONFIG(ONBOARD_LAN))
|
||||
{ // 1 - DISABLED
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED
|
||||
RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3
|
||||
}
|
||||
// else
|
||||
// { // 0 - AUTO
|
||||
// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
|
||||
// }
|
||||
|
||||
|
||||
//
|
||||
// Enable/Disable 1394
|
||||
//
|
||||
if (!CONFIG(ONBOARD_1394))
|
||||
{ // 1 - DISABLED
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE
|
||||
RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH
|
||||
}
|
||||
// else
|
||||
// { // 0 - AUTO
|
||||
// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
|
||||
//
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
|
||||
// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
|
||||
// }
|
||||
|
||||
//
|
||||
// external USB 3.0 control:
|
||||
// amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
|
||||
// GPIO26: PCIE_RST#_USB3.0
|
||||
// GPIO46: PCIE_USB30_CLKREQ#
|
||||
// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
|
||||
// Clock: GPP_CLK7
|
||||
// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
|
||||
// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
|
||||
// disable Onboard NEC USB3.0 controller
|
||||
if (!CONFIG(ONBOARD_USB30)) {
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE
|
||||
RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
|
||||
}
|
||||
// }
|
||||
|
||||
//
|
||||
// BlueTooth control: BT_ON
|
||||
// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
|
||||
// GPIO07: BT_ON, 0 - OFF, 1 - ON
|
||||
//
|
||||
if (!CONFIG(ONBOARD_BLUETOOTH)) {
|
||||
//- if (SystemConfiguration.amdBlueTooth == 1) {
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
|
||||
//- }
|
||||
}
|
||||
|
||||
//
|
||||
// WebCam control:
|
||||
// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
|
||||
// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
|
||||
//
|
||||
if (!CONFIG(ONBOARD_WEBCAM)) {
|
||||
//- if (SystemConfiguration.amdWebCam == 1) {
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
|
||||
//- }
|
||||
}
|
||||
|
||||
//
|
||||
// Travis enable:
|
||||
// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
|
||||
// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
|
||||
//
|
||||
if (!CONFIG(ONBOARD_TRAVIS)) {
|
||||
//- if (SystemConfiguration.amdTravisCtrl == 0) {
|
||||
RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
|
||||
//- }
|
||||
}
|
||||
|
||||
//
|
||||
// Disable Light Sensor if needed
|
||||
//
|
||||
if (CONFIG(ONBOARD_LIGHTSENSOR)) {
|
||||
//- if (SystemConfiguration.amdLightSensor == 1) {
|
||||
RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
|
||||
//- }
|
||||
}
|
||||
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,103 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = 0;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
|
||||
#define ONE_MB 0x100000
|
||||
//#define SMBUS_IO_BASE 0x6000
|
||||
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in torpedo board.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -1,232 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/mmio.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <southbridge/amd/cimx/sb900/SbPlatform.h>
|
||||
|
||||
#define IO_APIC_ID CONFIG_MAX_CPUS
|
||||
u32 apicid_sb900;
|
||||
|
||||
u8 picr_data[] = {
|
||||
0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x0B,0x0B,0x0B,0x0B
|
||||
};
|
||||
u8 intr_data[] = {
|
||||
0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x10,0x11,0x12,0x13
|
||||
};
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
int boot_apic_id;
|
||||
unsigned int apic_version;
|
||||
unsigned int cpu_features;
|
||||
unsigned int cpu_feature_flags;
|
||||
struct cpuid_result result;
|
||||
unsigned long cpu_flag;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
/*Inagua used dure core CPU with one die */
|
||||
boot_apic_id = lapicid();
|
||||
apic_version = lapic_read(LAPIC_LVR) & 0xff;
|
||||
result = cpuid(1);
|
||||
cpu_features = result.eax;
|
||||
cpu_feature_flags = result.edx;
|
||||
cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
|
||||
smp_write_processor(mc,
|
||||
0, apic_version,
|
||||
cpu_flag, cpu_features, cpu_feature_flags
|
||||
);
|
||||
|
||||
cpu_flag = MPC_CPU_ENABLED;
|
||||
smp_write_processor(mc,
|
||||
1, apic_version,
|
||||
cpu_flag, cpu_features, cpu_feature_flags
|
||||
);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
|
||||
u8 *dword;
|
||||
u8 byte;
|
||||
|
||||
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
|
||||
dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0);
|
||||
/* Set IO APIC ID onto IO_APIC_ID */
|
||||
write32 (dword, 0x00);
|
||||
write32 (dword + 0x10, IO_APIC_ID << 24);
|
||||
apicid_sb900 = IO_APIC_ID;
|
||||
smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
|
||||
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
outb(byte, 0xC00);
|
||||
outb(picr_data[byte], 0xC01);
|
||||
}
|
||||
|
||||
/* APIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
outb(intr_data[byte], 0xC01);
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
//mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
|
||||
/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1);
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb900, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb900, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb900, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb900, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb900, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb900, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb900, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb900, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb900, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb900, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb900, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb900, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb900, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb900, 0xf);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
|
||||
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,30 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PMIO_H_
|
||||
#define _PMIO_H_
|
||||
|
||||
#define PM_INDEX 0xCD6
|
||||
#define PM_DATA 0xCD7
|
||||
#define PM2_INDEX 0xCD0
|
||||
#define PM2_DATA 0xCD1
|
||||
|
||||
void pm_iowrite(u8 reg, u8 value);
|
||||
u8 pm_ioread(u8 reg);
|
||||
void pm2_iowrite(u8 reg, u8 value);
|
||||
u8 pm2_ioread(u8 reg);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
#include <superio/smsc/kbc1100/kbc1100.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
|
||||
|
||||
void board_BeforeAgesa(struct sysinfo *cb)
|
||||
{
|
||||
kbc1100_early_init(0x2e);
|
||||
kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
Loading…
Reference in New Issue