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cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 

Change-Id: I7e8866d76d7f286e10160d7dc4f21f01a913bfee
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6286
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-07-16 19:03:55 +10:00
parent 29794b7ad7
commit dc112e3515
13 changed files with 0 additions and 13 deletions
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1
src/cpu/amd/agesa/family10/Makefile.inc
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@ -301,4 +301,3 @@ subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/mtrr
subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm subdirs-y += ../../../x86/smm

1
src/cpu/amd/agesa/family15/Makefile.inc
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@ -27,4 +27,3 @@ subdirs-y += ../../../x86/smm
ramstage-y += chip_name.c ramstage-y += chip_name.c
ramstage-y += model_15_init.c ramstage-y += model_15_init.c

1
src/cpu/amd/geode_gx2/Makefile.inc
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@ -12,4 +12,3 @@ cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage vsa-type = stage
vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository) vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)

1
src/cpu/amd/geode_lx/Makefile.inc
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@ -12,4 +12,3 @@ cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage vsa-type = stage
vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository) vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)

1
src/cpu/intel/slot_1/Makefile.inc
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@ -33,4 +33,3 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

1
src/cpu/intel/slot_2/Makefile.inc
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@ -26,4 +26,3 @@ subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode

1
src/cpu/intel/socket_441/Makefile.inc
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@ -8,4 +8,3 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep

1
src/cpu/intel/socket_PGA370/Makefile.inc
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@ -28,4 +28,3 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

1
src/cpu/intel/socket_mPGA478/Makefile.inc
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@ -8,4 +8,3 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading

1
src/cpu/intel/socket_mPGA603/Makefile.inc
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@ -9,4 +9,3 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading

1
src/cpu/intel/socket_mPGA604/Makefile.inc
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@ -11,4 +11,3 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc

1
src/cpu/x86/name/Makefile.inc
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@ -18,4 +18,3 @@
## ##
ramstage-y += name.c ramstage-y += name.c

1
src/cpu/x86/tsc/Makefile.inc
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@ -3,4 +3,3 @@ romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
endif endif