nb/intel/sandybridge: Make the mainboard_early_init hook optional

This adds an empty weakly linked default. The rationale behind this
change is that without the callback some features might not work
but that the result is likely still able to boot, so it can be made
optional.

Change-Id: I62c8010aa81fc45d208e9293feb2f45b45f34a82
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/apple/macbookair4_2/romstage.c

@@ -49,10 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/asrock/b75pro3-m/romstage.c

@@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	/* Set GPIOs on superio, enable UART */

src/mainboard/asus/h61m-cs/romstage.c

@@ -52,10 +52,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	nuvoton_pnp_enter_conf_state(SIO_DEV);

src/mainboard/asus/maximus_iv_gene-z/romstage.c

@@ -48,10 +48,6 @@ void mainboard_rcba_config(void)
 {
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);

src/mainboard/asus/p8h61-m_lx/romstage.c

@@ -51,10 +51,6 @@ void mainboard_rcba_config(void)
 {
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p8h61-m_pro/romstage.c

@@ -53,10 +53,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	/* Enable UART */

src/mainboard/asus/p8z77-m_pro/romstage.c

@@ -56,10 +56,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 2, 6 }  /* Port 13: Unused. Asus propietary DEBUG_PORT ??? */
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	/* Setup COM/UART */

src/mainboard/compulab/intense_pc/romstage.c

@@ -60,10 +60,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	const u16 port = SIO_PORT;

src/mainboard/gigabyte/ga-b75m-d3h/romstage.c

@@ -78,10 +78,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 5, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 /* FIXME: The GA-B75M-D3V only has two DIMM slots! */
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 {

src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c

@@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	if (!CONFIG(NO_UART_ON_SUPERIO)) {

src/mainboard/google/butterfly/romstage.c

@@ -112,10 +112,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[2], 0x52, id_only);
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/google/parrot/romstage.c

@@ -84,10 +84,6 @@ void mainboard_rcba_config(void)
 	RCBA32(FD) = reg32;
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	struct pei_data pei_data_template = {

src/mainboard/hp/2570p/romstage.c

@@ -45,10 +45,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	kbc1126_enter_conf();

src/mainboard/hp/2760p/romstage.c

@@ -44,10 +44,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	kbc1126_enter_conf();

src/mainboard/hp/8460p/romstage.c

@@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 }, /* docking */
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/hp/8470p/romstage.c

@@ -47,10 +47,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/hp/8770w/romstage.c

@@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 }, /* Conn (eSATA Combo) */
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/hp/compaq_8200_elite_sff/romstage.c

@@ -52,10 +52,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	if (CONFIG(CONSOLE_SERIAL))

src/mainboard/hp/folio_9470m/romstage.c

@@ -46,10 +46,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 0, 6 }, /* B1P6 */
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	kbc1126_enter_conf();

src/mainboard/hp/revolve_810_g1/romstage.c

@@ -50,10 +50,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 0, 6 }, /* B1P6 */
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	kbc1126_enter_conf();

src/mainboard/hp/z220_sff_workstation/romstage.c

@@ -52,10 +52,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 7 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	if (CONFIG(CONSOLE_SERIAL))

src/mainboard/intel/dcp847ske/early_southbridge.c

@@ -52,10 +52,6 @@ void mainboard_rcba_config(void)
 	MCHBAR32(0x0104) |= 0x00001000;
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 static const u16 hwm_initvals[] = {
 	HWM_BANK(0),
 	HWM_INITVAL(0xae, 0x01), /* Enable PECI Agent0 */

src/mainboard/intel/emeraldlake2/romstage.c

@@ -153,10 +153,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[2], 0x52, id_only);
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 int mainboard_should_reset_usb(int s3resume)
 {
 	return !s3resume;

src/mainboard/lenovo/l520/romstage.c

@@ -47,10 +47,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/lenovo/s230u/romstage.c

@@ -64,10 +64,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/lenovo/t430s/variants/t431s/romstage.c

@@ -54,7 +54,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	memcpy(&spd[0], spd_file, spd_file_len);
 	read_spd(&spd[2], 0x51, id_only);
 }
-
-void mainboard_early_init(int s3resume)
-{
-}

src/mainboard/lenovo/x131e/romstage.c

@@ -51,10 +51,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[2], 0x52, id_only);
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/lenovo/x1_carbon_gen1/romstage.c

@@ -104,10 +104,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	memcpy(&spd[2], memory, 256);
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/lenovo/x220/romstage.c

@@ -91,10 +91,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd (&spd[2], 0x51, id_only);
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/lenovo/x230/romstage.c

@@ -56,10 +56,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd (&spd[2], 0x51, id_only);
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/msi/ms7707/romstage.c

@@ -49,10 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{1, 0, 6},
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/roda/rv11/romstage.c

@@ -27,10 +27,6 @@ void mainboard_rcba_config(void)
 	RCBA32(FD) = reg32;
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 int mainboard_should_reset_usb(int s3resume)
 {
 	return !s3resume;

src/mainboard/sapphire/pureplatinumh61/romstage.c

@@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/northbridge/intel/sandybridge/romstage.c

@@ -30,6 +30,10 @@
 #include <southbridge/intel/common/pmclib.h>
 #include <elog.h>
 
+__weak void mainboard_early_init(int s3_resume)
+{
+}
+
 static void early_pch_reset_pmcon(void)
 {
 	u8 reg8;

src/northbridge/intel/sandybridge/sandybridge.h

@@ -213,6 +213,8 @@ void northbridge_romstage_finalize(int s3resume);
 void early_init_dmi(void);
 
 void pch_enable_lpc(void);
+/* mainboard_early_init: Optional mainboard callback run after console init
+   but before raminit. */
 void mainboard_early_init(int s3resume);
 void mainboard_config_superio(void);
 int mainboard_should_reset_usb(int s3resume);