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Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-15 21:26:04 +00:00 committed by Marc Jones
parent 2b9143afcc
commit dc312cca53
3 changed files with 4 additions and 4 deletions
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2
src/mainboard/amd/persimmon/dsdt.asl
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@ -36,7 +36,7 @@ DefinitionBlock (
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(PCBA, 0xF8000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */

4
src/northbridge/amd/agesa_wrapper/family14/Kconfig
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@ -41,12 +41,12 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
default 0xf8000000
depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
config MMCONF_BUS_NUMBER
int
default 256
default 16
depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
config DIMM_DDR3

2
src/vendorcode/amd/cimx/sb800/OEM.h
View File

@ -48,7 +48,7 @@
#ifdef MOVE_PCIEBAR_TO_F0000000
#define PCIEX_BASE_ADDRESS 0xF7000000
#else
#define PCIEX_BASE_ADDRESS 0xE0000000
#define PCIEX_BASE_ADDRESS 0xF8000000
#endif
/**