mb/lenovo/g505s: Convert to ASL 2.0 syntax
Change-Id: I56f844706ba6bde3e57a6a81ff1d8e16863913f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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@ -15,7 +15,7 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* USB controller PME# */
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/* USB controller PME# */
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Method(_L0B) {
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Method(_L0B) {
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Store("USB PME", Debug)
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Debug = "USB PME"
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/* Notify devices of wake event */
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/* Notify devices of wake event */
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Notify(\_SB.PCI0.UOH1, 0x02)
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Notify(\_SB.PCI0.UOH1, 0x02)
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Notify(\_SB.PCI0.UOH2, 0x02)
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Notify(\_SB.PCI0.UOH2, 0x02)
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@ -37,16 +37,16 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* Lid switch opened or closed */
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/* Lid switch opened or closed */
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Method(_L16) {
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Method(_L16) {
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Store("Lid status changed", Debug)
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Debug = "Lid status changed"
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/* Flip trigger polarity */
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/* Flip trigger polarity */
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Not(LPOL, LPOL)
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LPOL = ~LPOL
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/* Notify lid object of status change */
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/* Notify lid object of status change */
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Notify(\_SB.LID, 0x80)
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Notify(\_SB.LID, 0x80)
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}
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}
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/* GPIO0 or GEvent8 event */
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/* GPIO0 or GEvent8 event */
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Method(_L18) {
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Method(_L18) {
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Store("PCI bridge wake event", Debug)
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Debug = "PCI bridge wake event"
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/* Notify PCI bridges of wake event */
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/* Notify PCI bridges of wake event */
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Notify(\_SB.PCI0.PBR4, 0x02)
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Notify(\_SB.PCI0.PBR4, 0x02)
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Notify(\_SB.PCI0.PBR5, 0x02)
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Notify(\_SB.PCI0.PBR5, 0x02)
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@ -56,7 +56,7 @@
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*/
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*/
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Method (PNOT)
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Method (PNOT)
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{
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{
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Store("Received PNOT call (probably from EC)", Debug)
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Debug = "Received PNOT call (probably from EC)"
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/* TODO: Implement this */
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/* TODO: Implement this */
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}
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}
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@ -75,7 +75,7 @@ Scope (\_SB) {
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/* Make sure lid trigger polarity is set so that we
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/* Make sure lid trigger polarity is set so that we
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* trigger an SCI when lid status changes.
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* trigger an SCI when lid status changes.
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*/
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*/
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Not(GE22, LPOL)
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LPOL = ~GE22
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}
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}
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}
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}
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@ -95,7 +95,7 @@ Scope (\_SB) {
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/* Toggle wireless */
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/* Toggle wireless */
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Method (WLTG)
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Method (WLTG)
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{
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{
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Store( Not(GP57), GP57 )
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GP57 = ~GP57
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}
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}
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/* Return lid state */
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/* Return lid state */
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Method (LIDS)
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Method (LIDS)
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@ -26,20 +26,20 @@ Method(\_PTS, 1) {
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/* DBGO("\n") */
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/* DBGO("\n") */
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/* Clear sleep SMI status flag and enable sleep SMI trap. */
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/* Clear sleep SMI status flag and enable sleep SMI trap. */
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/*Store(One, CSSM)
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/*CSSM = 1
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Store(One, SSEN)*/
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SSEN = 1*/
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/* On older chips, clear PciExpWakeDisEn */
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/* On older chips, clear PciExpWakeDisEn */
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/*if (LLessEqual(\_SB.SBRI, 0x13)) {
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/*if (\_SB.SBRI <= 0x13) {
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* Store(0,\_SB.PWDE)
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* \_SB.PWDE = 0
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*}
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*}
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*/
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*/
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/* Clear wake status structure. */
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/* Clear wake status structure. */
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Store(0, Index(WKST,0))
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WKST [0] = 0
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Store(0, Index(WKST,1))
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WKST [1] = 0
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Store (0x07, UPWS)
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UPWS = 0x07
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} /* End Method(\_PTS) */
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} /* End Method(\_PTS) */
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/*
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/*
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@ -64,7 +64,7 @@ Method(\_WAK, 1) {
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/* DBGO(" to S0\n") */
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/* DBGO(" to S0\n") */
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/* Re-enable HPET */
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/* Re-enable HPET */
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Store(1,USBS)
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USBS = 1
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Return(WKST)
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Return(WKST)
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} /* End Method(\_WAK) */
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} /* End Method(\_WAK) */
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