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AGESA,binaryPI: Split romstage_main() to BSP and AP parts 

BSP and AP have two distinct execution paths for romstage.

Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-11-28 15:04:17 +02:00
parent ce51d6d9d1
commit dc34a9d6de
2 changed files with 32 additions and 4 deletions
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34
src/drivers/amd/agesa/romstage.c
View File

@ -40,7 +40,7 @@ static void fill_sysinfo(struct sysinfo *cb)
agesa_set_interface(cb);
}
void *asmlinkage romstage_main(unsigned long bist)
static void bsp_romstage_main(unsigned long bist)
{
struct postcar_frame pcf;
struct sysinfo romstage_state;
@ -53,7 +53,7 @@ void *asmlinkage romstage_main(unsigned long bist)
fill_sysinfo(cb);
if ((initial_apic_id == 0) && boot_cpu()) {
if (initial_apic_id == 0) {
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
@ -101,5 +101,33 @@ void *asmlinkage romstage_main(unsigned long bist)
run_postcar_phase(&pcf);
/* We do not return. */
return NULL;
}
static void __noreturn ap_romstage_main(unsigned long bist)
{
struct sysinfo romstage_state;
struct sysinfo *cb = &romstage_state;
/* Enable PCI MMIO configuration. */
amd_initmmio();
fill_sysinfo(cb);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
agesa_execute_state(cb, AMD_INIT_RESET);
agesa_execute_state(cb, AMD_INIT_EARLY);
/* Not reached. */
halt();
}
asmlinkage void romstage_main(unsigned long bist)
{
if (boot_cpu())
bsp_romstage_main(bist);
else
ap_romstage_main(bist);
}

2
src/include/cpu/amd/car.h
View File

@ -3,6 +3,6 @@
#include <arch/cpu.h>
void *asmlinkage romstage_main(unsigned long bist);
asmlinkage void romstage_main(unsigned long bist);
#endif