AGESA,binaryPI: Split romstage_main() to BSP and AP parts
BSP and AP have two distinct execution paths for romstage. Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -40,7 +40,7 @@ static void fill_sysinfo(struct sysinfo *cb)
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agesa_set_interface(cb);
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agesa_set_interface(cb);
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}
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}
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void *asmlinkage romstage_main(unsigned long bist)
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static void bsp_romstage_main(unsigned long bist)
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{
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{
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struct postcar_frame pcf;
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struct postcar_frame pcf;
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struct sysinfo romstage_state;
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struct sysinfo romstage_state;
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@ -53,7 +53,7 @@ void *asmlinkage romstage_main(unsigned long bist)
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fill_sysinfo(cb);
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fill_sysinfo(cb);
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if ((initial_apic_id == 0) && boot_cpu()) {
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if (initial_apic_id == 0) {
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timestamp_init(timestamp_get());
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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timestamp_add_now(TS_START_ROMSTAGE);
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@ -101,5 +101,33 @@ void *asmlinkage romstage_main(unsigned long bist)
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run_postcar_phase(&pcf);
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run_postcar_phase(&pcf);
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/* We do not return. */
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/* We do not return. */
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return NULL;
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}
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static void __noreturn ap_romstage_main(unsigned long bist)
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{
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struct sysinfo romstage_state;
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struct sysinfo *cb = &romstage_state;
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/* Enable PCI MMIO configuration. */
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amd_initmmio();
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fill_sysinfo(cb);
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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agesa_execute_state(cb, AMD_INIT_RESET);
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agesa_execute_state(cb, AMD_INIT_EARLY);
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/* Not reached. */
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halt();
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}
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asmlinkage void romstage_main(unsigned long bist)
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{
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if (boot_cpu())
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bsp_romstage_main(bist);
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else
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ap_romstage_main(bist);
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}
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}
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@ -3,6 +3,6 @@
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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void *asmlinkage romstage_main(unsigned long bist);
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asmlinkage void romstage_main(unsigned long bist);
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#endif
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#endif
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