diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 8053fd1f06..336618aa01 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -33,9 +33,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam16.h>
 #include <arch/acpi.h>
-#if CONFIG_HAVE_ACPI_RESUME
-#include <cpu/amd/agesa/s3_resume.h>
-#endif
+#include <cpu/amd/pi/s3_resume.h>
 
 static void model_16_init(device_t dev)
 {
@@ -72,10 +70,8 @@ static void model_16_init(device_t dev)
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-#if CONFIG_HAVE_ACPI_RESUME
-	if (acpi_slp_type == 3)
+	if (acpi_is_wakeup())
 		restore_mtrr();
-#endif
 
 	x86_mtrr_check();
 	x86_enable_cache();
diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c
index d2c39312d5..aa251e07a4 100644
--- a/src/cpu/amd/pi/heapmanager.c
+++ b/src/cpu/amd/pi/heapmanager.c
@@ -1,7 +1,7 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
-#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
 #include "heapManager.h"
 
 #include <cbmem.h>
diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c
index fc619f7a34..bc82964cd2 100644
--- a/src/cpu/amd/pi/s3_resume.c
+++ b/src/cpu/amd/pi/s3_resume.c
@@ -31,7 +31,7 @@
 #include <arch/acpi.h>
 #include <string.h>
 #include "Porting.h"
-#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
 #include "s3_resume.h"
 
 /* The size needs to be 4k aligned, which is the sector size of most flashes. */