From dc357566ea715cd5dedd277046ff58c36b622dfd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 8 Jan 2015 20:44:30 +0200 Subject: [PATCH] cpu/amd/pi: Use acpi_is_wakeup() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Propagate commit 9107e53 from amd/agesa and fix some related #includes under cpu/amd/pi. Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8171 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/cpu/amd/pi/00730F01/model_16_init.c | 8 ++------ src/cpu/amd/pi/heapmanager.c | 2 +- src/cpu/amd/pi/s3_resume.c | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 8053fd1f06..336618aa01 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -33,9 +33,7 @@ #include #include #include -#if CONFIG_HAVE_ACPI_RESUME -#include -#endif +#include static void model_16_init(device_t dev) { @@ -72,10 +70,8 @@ static void model_16_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) + if (acpi_is_wakeup()) restore_mtrr(); -#endif x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index d2c39312d5..aa251e07a4 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -1,7 +1,7 @@ #include "AGESA.h" #include "amdlib.h" -#include +#include #include "heapManager.h" #include diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index fc619f7a34..bc82964cd2 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -31,7 +31,7 @@ #include #include #include "Porting.h" -#include +#include #include "s3_resume.h" /* The size needs to be 4k aligned, which is the sector size of most flashes. */