GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Various Debug Port southbridge implementation fixes / cosmetics.

Browse source 
- Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of
   hardcoding their values.
   
 - SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE.
 
 - ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC.
 
 - s/uint32_t/u32/.
 
 - Cosmetics, whitespace, coding style fixes and added code comments.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-09-25 23:47:15 +00:00
parent 86224f634a
commit dc3aa7abff
5 changed files with 98 additions and 65 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
src/southbridge/amd/sb600/sb600_enable_usbdebug.c
View file

@ -17,25 +17,30 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <stdint.h>
#include <usbdebug.h> #include <usbdebug.h>
#include <device/pci_def.h>
#ifndef SB600_DEVN_BASE #define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
#define SB600_DEVN_BASE 0 #define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */
#endif #define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */
#define EHCI_BAR_INDEX 0x10
#define EHCI_BAR 0xFEF00000
#define EHCI_DEBUG_OFFSET 0xE0
/* Required for successful build, but currently empty. */ /* Required for successful build, but currently empty. */
void set_debug_port(unsigned int port) void set_debug_port(unsigned int port)
{ {
/* TODO: Allow changing the physical USB port used as Debug Port. */
} }
static void sb600_enable_usbdebug(u32 port) static void sb600_enable_usbdebug(unsigned int port)
{ {
device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
/* Select the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port); set_debug_port(port);
pci_write_config32(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5),
EHCI_BAR_INDEX, EHCI_BAR); /* Set the EHCI BAR address. */
pci_write_config8(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enable */ pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }

27
src/southbridge/amd/sb700/sb700_enable_usbdebug.c
View file

@ -17,25 +17,30 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <stdint.h>
#include <usbdebug.h> #include <usbdebug.h>
#include <device/pci_def.h>
#ifndef SB700_DEVN_BASE #define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
#define SB700_DEVN_BASE 0 #define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */
#endif #define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */
#define EHCI_BAR_INDEX 0x10
#define EHCI_BAR 0xFEF00000
#define EHCI_DEBUG_OFFSET 0xE0
/* Required for successful build, but currently empty. */ /* Required for successful build, but currently empty. */
void set_debug_port(unsigned int port) void set_debug_port(unsigned int port)
{ {
/* TODO: Allow changing the physical USB port used as Debug Port. */
} }
static void sb700_enable_usbdebug(u32 port) static void sb700_enable_usbdebug(unsigned int port)
{ {
device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
/* Select the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port); set_debug_port(port);
pci_write_config32(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5),
EHCI_BAR_INDEX, EHCI_BAR); /* Set the EHCI BAR address. */
pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enable */ pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }

23
src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
View file

@ -17,16 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <stdint.h>
#include <usbdebug.h> #include <usbdebug.h>
#include <device/pci_def.h>
// An arbitrary address for the BAR #define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
#define EHCI_BAR 0xFEF00000 #define EHCI_BAR_INDEX 0x10 /* Hardwired 0x10 (>= ICH4). */
// These could be read from DEBUG_BASE (0:1d.7 R 0x5A 16bit) #define EHCI_DEBUG_OFFSET 0xA0 /* Hardwired 0xa0 (>= ICH5). */
#define EHCI_BAR_INDEX 0x10
#define EHCI_CONFIG_FLAG 0x40
#define EHCI_PORTSC 0x44
#define EHCI_DEBUG_OFFSET 0xA0
/* Required for successful build, but currently empty. */ /* Required for successful build, but currently empty. */
void set_debug_port(unsigned int port) void set_debug_port(unsigned int port)
@ -37,13 +34,17 @@ void set_debug_port(unsigned int port)
static void i82801gx_enable_usbdebug(unsigned int port) static void i82801gx_enable_usbdebug(unsigned int port)
{ {
u32 dbgctl; u32 dbgctl;
device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
pci_write_config32(PCI_DEV(0, 0x1d, 7), EHCI_BAR_INDEX, EHCI_BAR); /* Set the EHCI BAR address. */
pci_write_config8(PCI_DEV(0, 0x1d, 7), 0x04, 0x2); // Memory Space Enable pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */
printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET); dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30); dbgctl |= (1 << 30);
write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl); write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
} }

42
src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
View file

@ -21,32 +21,42 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <stdint.h>
#include <usbdebug.h>
#include <device/pci_def.h>
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else #else
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif #endif
#define EHCI_BAR_INDEX 0x10 #define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
#define EHCI_BAR 0xFEF00000 #define EHCI_BAR_INDEX 0x10
#define EHCI_DEBUG_OFFSET 0x98 #define EHCI_DEBUG_OFFSET 0x98
#include <usbdebug.h> void set_debug_port(unsigned int port)
void set_debug_port(unsigned port)
{ {
uint32_t dword; u32 dword;
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x74); device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
dword &= ~(0xf<<12);
dword |= (port<<12);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x74, dword);
/* Write the port number to 0x74[15:12]. */
dword = pci_read_config32(dev, 0x74);
dword &= ~(0xf << 12);
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
} }
static void mcp55_enable_usbdebug(unsigned port) static void mcp55_enable_usbdebug(unsigned int port)
{ {
device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
/* Mark the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port); set_debug_port(port);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), EHCI_BAR_INDEX, EHCI_BAR);
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x04, 0x2); // mem space enabe
}
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}

44
src/southbridge/sis/sis966/sis966_enable_usbdebug.c
View file

@ -21,32 +21,44 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/* TODO: Check whether this actually works (might be copy-paste leftover). */
#include <stdint.h>
#include <usbdebug.h>
#include <device/pci_def.h>
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else #else
#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif #endif
#define EHCI_BAR_INDEX 0x10 #define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
#define EHCI_BAR 0xFEF00000 #define EHCI_BAR_INDEX 0x10
#define EHCI_DEBUG_OFFSET 0x98 #define EHCI_DEBUG_OFFSET 0x98
#include <usbdebug.h> void set_debug_port(unsigned int port)
void set_debug_port(unsigned port)
{ {
uint32_t dword; u32 dword;
dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+2, 1), 0x74); device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
dword &= ~(0xf<<12);
dword |= (port<<12);
pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+2, 1), 0x74, dword);
/* Write the port number to 0x74[15:12]. */
dword = pci_read_config32(dev, 0x74);
dword &= ~(0xf << 12);
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
} }
static void sis966_enable_usbdebug(unsigned port) static void sis966_enable_usbdebug(unsigned int port)
{ {
device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
/* Mark the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port); set_debug_port(port);
pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+2, 1), EHCI_BAR_INDEX, EHCI_BAR);
pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+2, 1), 0x04, 0x2); // mem space enabe
}
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}