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sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary} 

Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes Haouas 2022-11-29 17:36:51 +01:00 committed by Felix Held
parent 87a98b55b2
commit dc3beea75d
21 changed files with 32 additions and 32 deletions
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4
src/mainboard/apple/macbook21/devicetree.cb
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@ -55,8 +55,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0x11000006" register "gpe0_en" = "0x11000006"
register "alt_gp_smi_en" = "0x1000" register "alt_gp_smi_en" = "0x1000"
register "ide_enable_primary" = "1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "1" register "ide_enable_secondary" = "true"
register "c4onc3_enable" = "1" register "c4onc3_enable" = "1"

2
src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
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@ -38,7 +38,7 @@ chip northbridge/intel/x4x # Northbridge
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "2" register "gpi13_routing" = "2"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "sata_ports_implemented" = "0x3" register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x440" register "gpe0_en" = "0x440"

2
src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
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@ -33,7 +33,7 @@ chip northbridge/intel/x4x # Northbridge
register "pirqg_routing" = "0x80" register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b" register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "gpe0_en" = "0x440" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x000c0291" # Superio HWM register "gen1_dec" = "0x000c0291" # Superio HWM

2
src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
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@ -33,7 +33,7 @@ chip northbridge/intel/x4x # Northbridge
register "pirqg_routing" = "0x80" register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b" register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "sata_ports_implemented" = "0x3" register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x440" register "gpe0_en" = "0x440"

2
src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb
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@ -31,7 +31,7 @@ chip northbridge/intel/x4x # Northbridge
register "pirqg_routing" = "0x80" register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b" register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "sata_ports_implemented" = "0x3" register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x440" register "gpe0_en" = "0x440"

2
src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
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@ -33,7 +33,7 @@ chip northbridge/intel/x4x # Northbridge
register "pirqg_routing" = "0x80" register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b" register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "gpe0_en" = "0x440" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x000c0291" # Superio HWM register "gen1_dec" = "0x000c0291" # Superio HWM

4
src/mainboard/asus/p5gc-mx/devicetree.cb
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@ -38,8 +38,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0" register "gpe0_en" = "0"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "false"
register "p_cnt_throttling_supported" = "0" register "p_cnt_throttling_supported" = "0"

2
src/mainboard/asus/p5qpl-am/devicetree.cb
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@ -29,7 +29,7 @@ chip northbridge/intel/x4x # Northbridge
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "gpe0_en" = "0x04000440" register "gpe0_en" = "0x04000440"
register "gen1_dec" = "0x00000295" # HWM register "gen1_dec" = "0x00000295" # HWM

4
src/mainboard/foxconn/g41s-k/devicetree.cb
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@ -31,8 +31,8 @@ chip northbridge/intel/x4x # Northbridge
register "gpe0_en" = "0x00000441" register "gpe0_en" = "0x00000441"
register "alt_gp_smi_en" = "0x0000" register "alt_gp_smi_en" = "0x0000"
register "ide_enable_primary" = "0x0" register "ide_enable_primary" = "false"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "false"
register "sata_ports_implemented" = "0x3" register "sata_ports_implemented" = "0x3"
register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO

4
src/mainboard/getac/p470/devicetree.cb
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@ -43,8 +43,8 @@ chip northbridge/intel/i945
register "alt_gp_smi_en" = "0x0100" register "alt_gp_smi_en" = "0x0100"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "false"
register "c3_latency" = "85" register "c3_latency" = "85"
register "docking_supported" = "1" register "docking_supported" = "1"

4
src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
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@ -61,8 +61,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0" register "gpe0_en" = "0"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "false"
register "c3_latency" = "85" register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0" register "p_cnt_throttling_supported" = "0"

4
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
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@ -32,8 +32,8 @@ chip northbridge/intel/x4x # Northbridge
register "pirqf_routing" = "0x0b" register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b" register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b" register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "false"
register "sata_ports_implemented" = "0x3" register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x40" register "gpe0_en" = "0x40"

4
src/mainboard/ibase/mb899/devicetree.cb
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@ -34,8 +34,8 @@ chip northbridge/intel/i945
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1" register "gpi13_routing" = "1"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "false"
register "c3_latency" = "85" register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0" register "p_cnt_throttling_supported" = "0"

4
src/mainboard/intel/d945gclf/devicetree.cb
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@ -36,8 +36,8 @@ chip northbridge/intel/i945
register "gpi13_routing" = "1" register "gpi13_routing" = "1"
register "gpe0_en" = "0x20000601" register "gpe0_en" = "0x20000601"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "false"
register "c3_latency" = "85" register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0" register "p_cnt_throttling_supported" = "0"

2
src/mainboard/intel/dg41wv/devicetree.cb
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@ -50,7 +50,7 @@ chip northbridge/intel/x4x # Northbridge
register "gpi14_routing" = "2" register "gpi14_routing" = "2"
register "gpi15_routing" = "2" register "gpi15_routing" = "2"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "gpe0_en" = "0x440" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x00fc0a01" # HWM register "gen1_dec" = "0x00fc0a01" # HWM

4
src/mainboard/kontron/986lcd-m/devicetree.cb
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@ -35,8 +35,8 @@ chip northbridge/intel/i945
register "gpi13_routing" = "1" register "gpi13_routing" = "1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "0x1" register "ide_enable_secondary" = "true"
register "c3_latency" = "85" register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0" register "p_cnt_throttling_supported" = "0"

2
src/mainboard/lenovo/t60/mainboard.c
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@ -34,7 +34,7 @@ static void mainboard_init(struct device *dev)
} else if (idedev && idedev->chip_info && } else if (idedev && idedev->chip_info &&
h8_ultrabay_device_present()) { h8_ultrabay_device_present()) {
config = idedev->chip_info; config = idedev->chip_info;
config->ide_enable_primary = 1; config->ide_enable_primary = true;
pmh7_ultrabay_power_enable(1); pmh7_ultrabay_power_enable(1);
ec_write(0x0c, 0x84); ec_write(0x0c, 0x84);
} else { } else {

2
src/mainboard/lenovo/thinkcentre_a58/devicetree.cb
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@ -31,7 +31,7 @@ chip northbridge/intel/x4x # Northbridge
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1" # ??vendor register "gpi13_routing" = "1" # ??vendor
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "gpe0_en" = "0x440" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x00fc0a01" register "gen1_dec" = "0x00fc0a01"

2
src/mainboard/lenovo/x60/mainboard.c
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@ -37,7 +37,7 @@ static void mainboard_init(struct device *dev)
idedev = pcidev_on_root(0x1f, 1); idedev = pcidev_on_root(0x1f, 1);
if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
struct southbridge_intel_i82801gx_config *config = idedev->chip_info; struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
config->ide_enable_primary = 1; config->ide_enable_primary = true;
/* enable Ultrabay power */ /* enable Ultrabay power */
outb(inb(0x1628) | 0x01, 0x1628); outb(inb(0x1628) | 0x01, 0x1628);
ec_write(0x0c, 0x84); ec_write(0x0c, 0x84);

4
src/mainboard/roda/rk886ex/devicetree.cb
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@ -46,8 +46,8 @@ chip northbridge/intel/i945
register "p_cnt_throttling_supported" = "1" register "p_cnt_throttling_supported" = "1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "false"
register "gen1_dec" = "0x001c02e1" # COM3, COM4 register "gen1_dec" = "0x001c02e1" # COM3, COM4
register "gen2_dec" = "0x00fc0601" # ?? register "gen2_dec" = "0x00fc0601" # ??

4
src/southbridge/intel/i82801gx/chip.h
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@ -55,8 +55,8 @@ struct southbridge_intel_i82801gx_config {
uint16_t alt_gp_smi_en; uint16_t alt_gp_smi_en;
/* IDE configuration */ /* IDE configuration */
uint32_t ide_enable_primary; bool ide_enable_primary;
uint32_t ide_enable_secondary; bool ide_enable_secondary;
enum sata_mode sata_mode; enum sata_mode sata_mode;
uint32_t sata_ports_implemented; uint32_t sata_ports_implemented;