soc/intel/quark: Pass in the memory initialization parameters
Specify the memory initialization parameters in mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to initialize memory. TEST=Build and run on Galileo Gen2 Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15260 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
parent
5d94c26653
commit
dc54270210
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@ -3,7 +3,7 @@
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<title>Galileo Implementation Status</title>
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</title>
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<body>
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<h1>Galileo Implementation Status<br>2016/06/08 17:18:24 PDT</h1>
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<h1>Galileo Implementation Status<br>2016/07/08 06:51:34 PDT</h1>
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<table>
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<tr><td colspan=2><b>Legend</b></td></tr>
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<tr><td bgcolor="#ffc0c0">Red</td><td>Required - To-be-implemented</td></tr>
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@ -31,7 +31,7 @@
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<td width=5> </td>
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<td>
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<table border=1>
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<tr><th colspan=2>romstage: 66% Done</th></tr>
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<tr><th colspan=2>romstage: 67% Done</th></tr>
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<tr><th>Type</th><th>Routine</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr>
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@ -78,7 +78,7 @@
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<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region</td></tr>
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<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_memory_init_params</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr>
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@ -98,7 +98,7 @@
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<td width=5> </td>
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<td>
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<table border=1>
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<tr><th colspan=2>ramstage: 55% Done</th></tr>
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<tr><th colspan=2>ramstage: 60% Done</th></tr>
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<tr><th>Type</th><th>Routine</td></tr>
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<tr bgcolor=#ffc0c0><td>Required</td><td>acpi_create_serialio_ssdt</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr>
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@ -138,7 +138,7 @@
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<tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_silicon_init_params</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_silicon_init_params</td></tr>
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<tr bgcolor=#ffc0c0><td>Required</td><td>soc_fill_acpi_wake</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_silicon_init_params</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>soc_skip_ucode_update</td></tr>
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@ -20,7 +20,32 @@ chip soc/intel/quark
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# Set the parameters for MemoryInit
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############################################################
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register "PcdSmmTsegSize" = "0" # SMM Region size in MiB
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register "AddrMode" = "0"
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register "ChanMask" = "1" # Channel 0 enabled
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register "ChanWidth" = "1" # 16-bit channel
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register "DramDensity" = "1" # 1 Gib;
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register "DramRonVal" = "0" # 34 Ohm
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register "DramRttNomVal" = "2" # 120 Ohm
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register "DramRttWrVal" = "0" # off
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register "DramSpeed" = "0" # 800 MHz
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register "DramType" = "0" # DDR3
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register "DramWidth" = "0" # 8-bit
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register "EccScrubBlkSize" = "2" # 64 byte blocks
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register "EccScrubInterval" = "0" # ECC scrub disabled
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register "Flags" = "MRC_FLAG_SCRAMBLE_EN"
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register "FspReservedMemoryLength" = "0x00100000" # Size in bytes
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register "RankMask" = "1" # RANK 0 enabled
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register "SmmTsegSize" = "0" # SMM Region size in MiB
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register "SocRdOdtVal" = "0" # off
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register "SocWrRonVal" = "1" # 32 Ohm
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register "SocWrSlewRate" = "1" # 4V/nSec
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register "SrInt" = "3" # 7.8 uSec
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register "SrTemp" = "0" # normal
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register "tCL" = "6" # clocks
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register "tFAW" = "40000" # picoseconds
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register "tRAS" = "37500" # picoseconds
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register "tRRD" = "10000" # picoseconds
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register "tWTR" = "10000" # picoseconds
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############################################################
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# Enable the devices
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@ -23,6 +23,19 @@
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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///
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/// MRC Flags bits
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///
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#define MRC_FLAG_ECC_EN BIT0
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#define MRC_FLAG_SCRAMBLE_EN BIT1
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#define MRC_FLAG_MEMTEST_EN BIT2
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/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
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#define MRC_FLAG_TOP_TREE_EN BIT3
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/* If set ODR signal is asserted to DRAM devices on writes */
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#define MRC_FLAG_WR_ODT_EN BIT4
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struct soc_intel_quark_config {
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/*
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* MemoryInit:
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@ -33,7 +46,71 @@ struct soc_intel_quark_config {
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* built into the coreboot image. The fields below contain retain
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* the FSP PCD field name.
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*/
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UINT16 PcdSmmTsegSize;
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UINT32 FspReservedMemoryLength; /* FSP reserved memory in bytes */
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UINT32 Flags; /* Bitmap of MRC_FLAG_XXX defs above */
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UINT32 tRAS; /* ACT to PRE command period in picoseconds */
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/* Delay from start of internal write transaction to internal read
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* command in picoseconds
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*/
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UINT32 tWTR;
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/* ACT to ACT command period (JESD79 specific to page size 1K/2K) in
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* picoseconds
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*/
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UINT32 tRRD;
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/* Four activate window (JESD79 specific to page size 1K/2K) in
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* picoseconds
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*/
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UINT32 tFAW;
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UINT8 DramWidth; /* 0=x8, 1=x16, others=RESERVED */
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/* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU
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* support 1066 memory
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*/
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UINT8 DramSpeed;
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UINT8 DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */
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/* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */
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UINT8 RankMask;
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UINT8 ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */
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UINT8 ChanWidth; /* 1=x16, others=RESERVED */
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/* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */
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UINT8 AddrMode;
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/* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */
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UINT8 SrInt;
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UINT8 SrTemp; /* 0=normal, 1=extended, others=RESERVED */
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/* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver
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* impedance control.
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*/
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UINT8 DramRonVal;
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UINT8 DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
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UINT8 DramRttWrVal; /* 0=off others=RESERVED */
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/* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
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UINT8 SocRdOdtVal;
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UINT8 SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */
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UINT8 SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */
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/* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */
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UINT8 DramDensity;
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UINT8 tCL; /* DRAM CAS Latency in clocks */
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/* ECC scrub interval in miliseconds 1..255 (0 works as feature
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* disable)
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*/
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UINT8 EccScrubInterval;
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/* Number of 32B blocks read for ECC scrub 2..16 */
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UINT8 EccScrubBlkSize;
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UINT8 SmmTsegSize; /* SMM size in MiB */
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};
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extern struct chip_operations soc_ops;
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@ -129,6 +129,8 @@ void soc_memory_init_params(struct romstage_params *params,
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const struct device *dev;
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const struct soc_intel_quark_config *config;
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struct chipset_power_state *ps = car_get_var_ptr(&power_state);
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char *rmu_file;
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size_t rmu_file_len;
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/* Locate the configuration data from devicetree.cb */
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dev = dev_find_slot(0, LPC_DEV_FUNC);
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@ -150,11 +152,44 @@ void soc_memory_init_params(struct romstage_params *params,
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reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events);
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}
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/* Locate the RMU data file in flash */
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rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW,
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&rmu_file_len);
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if (!rmu_file)
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die("Microcode file (rmu.bin) not found.");
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/* Update the UPD data for MemoryInit */
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printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd);
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upd->PcdSerialRegisterBase = UART_BASE_ADDRESS;
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upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
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config->PcdSmmTsegSize : 0;
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upd->AddrMode = config->AddrMode;
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upd->ChanMask = config->ChanMask;
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upd->ChanWidth = config->ChanWidth;
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upd->DramDensity = config->DramDensity;
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upd->DramRonVal = config->DramRonVal;
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upd->DramRttNomVal = config->DramRttNomVal;
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upd->DramRttWrVal = config->DramRttWrVal;
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upd->DramSpeed = config->DramSpeed;
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upd->DramType = config->DramType;
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upd->DramWidth = config->DramWidth;
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upd->EccScrubBlkSize = config->EccScrubBlkSize;
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upd->EccScrubInterval = config->EccScrubInterval;
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upd->Flags = config->Flags;
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upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
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upd->RankMask = config->RankMask;
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upd->RmuBaseAddress = (uintptr_t)rmu_file;
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upd->RmuLength = rmu_file_len;
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upd->SerialPortBaseAddress = UART_BASE_ADDRESS;
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upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
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config->SmmTsegSize : 0;
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upd->SocRdOdtVal = config->SocRdOdtVal;
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upd->SocWrRonVal = config->SocWrRonVal;
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upd->SocWrSlewRate = config->SocWrSlewRate;
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upd->SrInt = config->SrInt;
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upd->SrTemp = config->SrTemp;
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upd->tCL = config->tCL;
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upd->tFAW = config->tFAW;
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upd->tRAS = config->tRAS;
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upd->tRRD = config->tRRD;
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upd->tWTR = config->tWTR;
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}
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void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
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@ -162,11 +197,61 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
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{
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/* Display the parameters for MemoryInit */
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printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new);
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fsp_display_upd_value("PcdSerialRegisterBase",
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sizeof(old->PcdSerialRegisterBase),
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old->PcdSerialRegisterBase, new->PcdSerialRegisterBase);
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fsp_display_upd_value("PcdSmmTsegSize", sizeof(old->PcdSmmTsegSize),
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old->PcdSmmTsegSize, new->PcdSmmTsegSize);
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fsp_display_upd_value("AddrMode", sizeof(old->AddrMode),
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old->AddrMode, new->AddrMode);
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fsp_display_upd_value("ChanMask", sizeof(old->ChanMask),
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old->ChanMask, new->ChanMask);
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fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth),
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old->ChanWidth, new->ChanWidth);
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fsp_display_upd_value("DramDensity", sizeof(old->DramDensity),
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old->DramDensity, new->DramDensity);
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fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal),
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old->DramRonVal, new->DramRonVal);
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fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal),
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old->DramRttNomVal, new->DramRttNomVal);
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fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal),
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old->DramRttWrVal, new->DramRttWrVal);
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fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed),
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old->DramSpeed, new->DramSpeed);
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fsp_display_upd_value("DramType", sizeof(old->DramType),
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old->DramType, new->DramType);
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fsp_display_upd_value("DramWidth", sizeof(old->DramWidth),
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old->DramWidth, new->DramWidth);
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fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize),
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old->EccScrubBlkSize, new->EccScrubBlkSize);
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fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval),
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old->EccScrubInterval, new->EccScrubInterval);
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fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags,
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new->Flags);
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fsp_display_upd_value("FspReservedMemoryLength",
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sizeof(old->FspReservedMemoryLength),
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old->FspReservedMemoryLength, new->FspReservedMemoryLength);
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fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask,
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new->RankMask);
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fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress),
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old->RmuBaseAddress, new->RmuBaseAddress);
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fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
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old->RmuLength, new->RmuLength);
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fsp_display_upd_value("SerialPortBaseAddress",
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sizeof(old->SerialPortBaseAddress),
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old->SerialPortBaseAddress, new->SerialPortBaseAddress);
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fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
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old->SmmTsegSize, new->SmmTsegSize);
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fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
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old->SocRdOdtVal, new->SocRdOdtVal);
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fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal),
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old->SocWrRonVal, new->SocWrRonVal);
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fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate),
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old->SocWrSlewRate, new->SocWrSlewRate);
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fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt,
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new->SrInt);
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fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp,
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new->SrTemp);
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fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL);
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fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW);
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fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS);
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fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD);
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fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR);
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}
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void soc_after_ram_init(struct romstage_params *params)
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@ -85,29 +85,110 @@ typedef struct {
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UINT64 Revision;
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/** Offset 0x0028
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**/
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UINT32 PcdRmuBinaryBaseAddress;
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UINT32 RmuBaseAddress;
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/** Offset 0x002C
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**/
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UINT32 UnusedUpdSpace0;
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UINT32 RmuLength;
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/** Offset 0x0030
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**/
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UINT32 PcdSerialRegisterBase;
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UINT32 SerialPortBaseAddress;
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/** Offset 0x0034
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**/
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UINT8 PcdSmmTsegSize;
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/** Offset 0x0035
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UINT32 tRAS;
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/** Offset 0x0038
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**/
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UINT8 ReservedMemoryInitUpd[3];
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UINT32 tWTR;
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/** Offset 0x003C
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**/
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UINT32 tRRD;
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/** Offset 0x0040
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**/
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UINT32 tFAW;
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/** Offset 0x0044
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**/
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UINT32 Flags;
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/** Offset 0x0048
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**/
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UINT8 DramWidth;
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/** Offset 0x0049
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**/
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UINT8 DramSpeed;
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/** Offset 0x004A
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**/
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UINT8 DramType;
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/** Offset 0x004B
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**/
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UINT8 RankMask;
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/** Offset 0x004C
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**/
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UINT8 ChanMask;
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/** Offset 0x004D
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**/
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UINT8 ChanWidth;
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/** Offset 0x004E
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**/
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UINT8 AddrMode;
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/** Offset 0x004F
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**/
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UINT8 SrInt;
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/** Offset 0x0050
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**/
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UINT8 SrTemp;
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/** Offset 0x0051
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**/
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UINT8 DramRonVal;
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/** Offset 0x0052
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**/
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UINT8 DramRttNomVal;
|
||||
/** Offset 0x0053
|
||||
**/
|
||||
UINT8 DramRttWrVal;
|
||||
/** Offset 0x0054
|
||||
**/
|
||||
UINT8 SocRdOdtVal;
|
||||
/** Offset 0x0055
|
||||
**/
|
||||
UINT8 SocWrRonVal;
|
||||
/** Offset 0x0056
|
||||
**/
|
||||
UINT8 SocWrSlewRate;
|
||||
/** Offset 0x0057
|
||||
**/
|
||||
UINT8 DramDensity;
|
||||
/** Offset 0x0058
|
||||
**/
|
||||
UINT8 tCL;
|
||||
/** Offset 0x0059
|
||||
**/
|
||||
UINT8 EccScrubInterval;
|
||||
/** Offset 0x005A
|
||||
**/
|
||||
UINT8 EccScrubBlkSize;
|
||||
/** Offset 0x005B
|
||||
**/
|
||||
UINT8 SmmTsegSize;
|
||||
/** Offset 0x005C
|
||||
**/
|
||||
UINT32 FspReservedMemoryLength;
|
||||
/** Offset 0x0060
|
||||
**/
|
||||
UINT32 MrcDataPtr;
|
||||
/** Offset 0x0064
|
||||
**/
|
||||
UINT32 MrcDataLength;
|
||||
/** Offset 0x0068
|
||||
**/
|
||||
UINT8 ReservedMemoryInitUpd[8];
|
||||
} MEMORY_INIT_UPD;
|
||||
|
||||
typedef struct {
|
||||
/** Offset 0x0038
|
||||
/** Offset 0x0070
|
||||
**/
|
||||
UINT64 Signature;
|
||||
/** Offset 0x0040
|
||||
/** Offset 0x0078
|
||||
**/
|
||||
UINT64 Revision;
|
||||
/** Offset 0x0048
|
||||
/** Offset 0x0080
|
||||
**/
|
||||
UINT16 PcdRegionTerminator;
|
||||
} SILICON_INIT_UPD;
|
||||
|
|
@ -132,7 +213,7 @@ typedef struct _UPD_DATA_REGION {
|
|||
/** Offset 0x0018
|
||||
**/
|
||||
MEMORY_INIT_UPD MemoryInitUpd;
|
||||
/** Offset 0x0038
|
||||
/** Offset 0x0070
|
||||
**/
|
||||
SILICON_INIT_UPD SiliconInitUpd;
|
||||
} UPD_DATA_REGION;
|
||||
|
|
|
|||
Loading…
Reference in New Issue