nb/intel/sandybridge: Rewrite magic numbers
Use bitwise negations for AND-masks and shifts for bitfields. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Id265728c362a5035ac57f84766e883608f29c398 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47511 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
9f58bb21a7
commit
dc5539fe16
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@ -27,9 +27,9 @@ static void sfence(void)
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static void toggle_io_reset(void)
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{
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u32 r32 = MCHBAR32(MC_INIT_STATE_G);
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MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20;
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MCHBAR32(MC_INIT_STATE_G) = r32 | (1 << 5);
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udelay(1);
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MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20;
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MCHBAR32(MC_INIT_STATE_G) = r32 & ~(1 << 5);
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udelay(1);
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}
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@ -130,11 +130,11 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
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stretch = 3;
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addr = SCHED_SECOND_CBIT_ch(channel);
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MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10));
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MCHBAR32_AND_OR(addr, ~(0xf << 10), (stretch << 12) | (stretch << 10));
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printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr));
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} else {
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addr = TC_OTHP_ch(channel);
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MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18));
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MCHBAR32_AND_OR(addr, ~(0xf << 16), (stretch << 16) | (stretch << 18));
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printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr));
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}
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}
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@ -211,7 +211,7 @@ void dram_timing_regs(ramctr_timing *ctrl)
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printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg);
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MCHBAR32(TC_RFTP_ch(channel)) = reg;
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MCHBAR32_OR(TC_RFP_ch(channel), 0xff);
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MCHBAR32_OR(TC_RFP_ch(channel), 0xff);
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/* Self-refresh timing parameters */
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reg = 0;
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@ -564,19 +564,19 @@ void dram_jedecreset(ramctr_timing *ctrl)
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MCHBAR32(MC_INIT_STATE_G) = reg;
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/* Assert DIMM reset signal */
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MCHBAR32_AND(MC_INIT_STATE_G, ~2);
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MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 1));
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/* Wait 200us */
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udelay(200);
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/* Deassert DIMM reset signal */
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MCHBAR32_OR(MC_INIT_STATE_G, 2);
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MCHBAR32_OR(MC_INIT_STATE_G, 1 << 1);
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/* Wait 500us */
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udelay(500);
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/* Enable DCLK */
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MCHBAR32_OR(MC_INIT_STATE_G, 4);
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MCHBAR32_OR(MC_INIT_STATE_G, 1 << 2);
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/* XXX Wait 20ns */
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udelay(1);
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@ -691,7 +691,7 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank)
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const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE;
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/* DLL Reset - self clearing - set after CLK frequency has been changed */
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mr0reg = 0x100;
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mr0reg = 1 << 8;
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/* Convert CAS to MCH register friendly */
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if (ctrl->CAS < 12) {
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@ -857,10 +857,10 @@ void dram_mrscommands(ramctr_timing *ctrl)
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}
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/* Refresh enable */
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MCHBAR32_OR(MC_INIT_STATE_G, 8);
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MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3);
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FOR_ALL_POPULATED_CHANNELS {
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MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000);
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MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21));
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wait_for_iosav(channel);
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@ -949,7 +949,7 @@ void program_timings(ramctr_timing *ctrl, int channel)
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MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay;
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reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel));
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reg_io_latency &= 0xffff0000;
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reg_io_latency &= ~0xffff;
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reg_roundtrip_latency = 0;
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@ -1663,7 +1663,7 @@ static void precharge(ramctr_timing *ctrl)
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static void test_timB(ramctr_timing *ctrl, int channel, int slotrank)
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{
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/* enable DQs on this slotrank */
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write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel));
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write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 7);
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wait_for_iosav(channel);
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@ -1715,7 +1715,8 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank)
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wait_for_iosav(channel);
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/* disable DQs on this slotrank */
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write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel));
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write_mrreg(ctrl, channel, slotrank, 1,
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make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7);
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}
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static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank)
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@ -1933,15 +1934,15 @@ int write_training(ramctr_timing *ctrl)
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int err;
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FOR_ALL_POPULATED_CHANNELS
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MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000);
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MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27);
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FOR_ALL_POPULATED_CHANNELS {
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write_op(ctrl, channel);
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MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000);
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MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21);
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}
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/* Refresh disable */
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MCHBAR32_AND(MC_INIT_STATE_G, ~8);
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MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3));
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FOR_ALL_POPULATED_CHANNELS {
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write_op(ctrl, channel);
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}
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@ -1951,7 +1952,7 @@ int write_training(ramctr_timing *ctrl)
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Only NOP is allowed in this mode */
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
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write_mrreg(ctrl, channel, slotrank, 1,
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make_mr1(ctrl, slotrank, channel) | 0x1080);
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make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7);
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MCHBAR32(GDCRTRAININGMOD) = 0x108052;
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@ -1974,10 +1975,10 @@ int write_training(ramctr_timing *ctrl)
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wait_for_iosav(channel);
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/* Refresh enable */
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MCHBAR32_OR(MC_INIT_STATE_G, 8);
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MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3);
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FOR_ALL_POPULATED_CHANNELS {
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MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000);
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MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21));
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MCHBAR32(IOSAV_STATUS_ch(channel));
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wait_for_iosav(channel);
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@ -2121,11 +2122,11 @@ static void reprogram_320c(ramctr_timing *ctrl)
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iosav_run_once(channel);
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wait_for_iosav(channel);
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MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000);
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MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21);
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}
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/* refresh disable */
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MCHBAR32_AND(MC_INIT_STATE_G, ~8);
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MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3));
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FOR_ALL_POPULATED_CHANNELS {
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wait_for_iosav(channel);
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@ -2891,7 +2892,7 @@ void set_scrambling_seed(ramctr_timing *ctrl)
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{0x00028bfa, 0x53fe4b49, 0x19ed5483}
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};
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FOR_ALL_POPULATED_CHANNELS {
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MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000;
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MCHBAR32(SCHED_CBIT_ch(channel)) &= ~(1 << 28);
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MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0];
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MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1];
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MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2];
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@ -2913,7 +2914,7 @@ void prepare_training(ramctr_timing *ctrl)
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FOR_ALL_POPULATED_CHANNELS {
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/* Always drive command bus */
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MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000);
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MCHBAR32_OR(TC_RAP_ch(channel), 1 << 29);
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}
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udelay(1);
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@ -2943,7 +2944,7 @@ void set_read_write_timings(ramctr_timing *ctrl)
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dram_odt_stretch(ctrl, channel);
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MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) |
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MCHBAR32(TC_RWP_ch(channel)) = (1 << 27) | (2 << 24) | (b20 << 20) |
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((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12;
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}
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}
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@ -2952,8 +2953,8 @@ void set_normal_operation(ramctr_timing *ctrl)
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{
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int channel;
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FOR_ALL_POPULATED_CHANNELS {
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MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel];
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MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000);
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MCHBAR32(MC_INIT_STATE_ch(channel)) = (1 << 12) | ctrl->rankmap[channel];
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MCHBAR32_AND(TC_RAP_ch(channel), ~(1 << 29));
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}
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}
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@ -2977,7 +2978,7 @@ void final_registers(ramctr_timing *ctrl)
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MCHBAR32(WMM_READ_CONFIG) = 0x46;
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FOR_ALL_CHANNELS
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MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000);
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MCHBAR32_AND_OR(TC_OTHP_ch(channel), ~(3 << 12), 1 << 12);
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if (is_mobile)
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/* APD - DLL Off, 64 DCLKs until idle, decision per rank */
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@ -3018,8 +3019,8 @@ void final_registers(ramctr_timing *ctrl)
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FOR_ALL_CHANNELS
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MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16);
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MCHBAR32_OR(MC_INIT_STATE_G, 1);
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MCHBAR32_OR(MC_INIT_STATE_G, 0x80);
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MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0);
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MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7);
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MCHBAR32(BANDTIMERS_SNB) = 0xfa;
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/* Find a populated channel */
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@ -3045,7 +3046,7 @@ void final_registers(ramctr_timing *ctrl)
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/* The graphics driver will use these watermark values */
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printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns);
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MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0,
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MCHBAR32_AND_OR(SSKPD, ~0x3f3f3f3f,
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((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) |
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((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c);
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}
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@ -3076,11 +3077,11 @@ void restore_timings(ramctr_timing *ctrl)
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}
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FOR_ALL_POPULATED_CHANNELS
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MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000);
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MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27);
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FOR_ALL_POPULATED_CHANNELS {
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udelay(1);
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MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000);
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MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21);
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}
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printram("CPE\n");
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