soc/intel/broadwell: Move `pei_data` out of romstage.c
Prepare to confine all `pei_data` references in raminit.c and refcode.c so that mainboards don't need to know about its existence. Change-Id: I55793fa274f8100643855466b6cca486896fb2c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55801 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -8,14 +8,12 @@
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void mainboard_fill_spd_data(struct pei_data *pei_data);
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void mainboard_post_raminit(const int s3resume);
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void sdram_initialize(struct pei_data *pei_data);
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void save_mrc_data(struct pei_data *pei_data);
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void setup_sdram_meminfo(struct pei_data *pei_data);
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struct chipset_power_state;
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struct chipset_power_state *fill_power_state(void);
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void report_platform_info(void);
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void perform_raminit(const struct chipset_power_state *const power_state);
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void systemagent_early_init(void);
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void pch_early_init(void);
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@ -15,8 +15,9 @@
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#include <soc/pm.h>
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#include <soc/romstage.h>
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#include <soc/systemagent.h>
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#include <timestamp.h>
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void save_mrc_data(struct pei_data *pei_data)
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static void save_mrc_data(struct pei_data *pei_data)
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{
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printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
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pei_data->data_to_save_size);
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@ -80,7 +81,7 @@ static void report_memory_config(void)
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/*
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* Find PEI executable in coreboot filesystem and execute it.
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*/
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void sdram_initialize(struct pei_data *pei_data)
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static void sdram_initialize(struct pei_data *pei_data)
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{
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size_t mrc_size;
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pei_wrapper_entry_t entry;
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@ -137,7 +138,7 @@ void sdram_initialize(struct pei_data *pei_data)
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report_memory_config();
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}
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void setup_sdram_meminfo(struct pei_data *pei_data)
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static void setup_sdram_meminfo(struct pei_data *pei_data)
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{
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struct memory_info *mem_info;
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@ -175,3 +176,35 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
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dimm->bus_width = pei_dimm->bus_width;
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}
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}
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void perform_raminit(const struct chipset_power_state *const power_state)
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{
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const int s3resume = power_state->prev_sleep_state == ACPI_S3;
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struct pei_data pei_data = { 0 };
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mainboard_fill_pei_data(&pei_data);
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mainboard_fill_spd_data(&pei_data);
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post_code(0x32);
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timestamp_add_now(TS_BEFORE_INITRAM);
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pei_data.boot_mode = power_state->prev_sleep_state;
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/* Initialize RAM */
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sdram_initialize(&pei_data);
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timestamp_add_now(TS_AFTER_INITRAM);
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int cbmem_was_initted = !cbmem_recovery(s3resume);
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if (s3resume && !cbmem_was_initted) {
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/* Failed S3 resume, reset to come up cleanly */
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printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
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system_reset();
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}
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save_mrc_data(&pei_data);
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setup_sdram_meminfo(&pei_data);
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}
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@ -9,13 +9,10 @@
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#include <elog.h>
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#include <romstage_handoff.h>
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#include <soc/me.h>
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#include <soc/pei_data.h>
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#include <soc/pei_wrapper.h>
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#include <soc/pm.h>
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#include <soc/romstage.h>
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#include <southbridge/intel/lynxpoint/lp_gpio.h>
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#include <stdint.h>
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#include <timestamp.h>
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__weak void mainboard_fill_spd_data(struct pei_data *pei_data)
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{
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@ -28,8 +25,6 @@ __weak void mainboard_post_raminit(const int s3resume)
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/* Entry from cpu/intel/car/romstage.c. */
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void mainboard_romstage_entry(void)
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{
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struct pei_data pei_data = { 0 };
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post_code(0x30);
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/* System Agent Early Initialization */
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@ -61,30 +56,7 @@ void mainboard_romstage_entry(void)
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intel_me_hsio_version(&power_state->hsio_version,
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&power_state->hsio_checksum);
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mainboard_fill_pei_data(&pei_data);
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mainboard_fill_spd_data(&pei_data);
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post_code(0x32);
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timestamp_add_now(TS_BEFORE_INITRAM);
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pei_data.boot_mode = power_state->prev_sleep_state;
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/* Initialize RAM */
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sdram_initialize(&pei_data);
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timestamp_add_now(TS_AFTER_INITRAM);
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int cbmem_was_initted = !cbmem_recovery(s3resume);
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if (s3resume && !cbmem_was_initted) {
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/* Failed S3 resume, reset to come up cleanly */
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printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
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system_reset();
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}
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save_mrc_data(&pei_data);
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setup_sdram_meminfo(&pei_data);
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perform_raminit(power_state);
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romstage_handoff_init(s3resume);
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