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cpu/intel/car: Use symbols for CAR MTRR setup 

Change-Id: I32d7337ccf8005c7fb65d2efea40c122093d4dd9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2019-11-08 00:08:55 +02:00 committed by Nico Huber
parent ed318f2001
commit dc6bb6cb82
4 changed files with 50 additions and 62 deletions
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27
src/cpu/intel/car/core2/cache_as_ram.S
View File

@ -4,14 +4,6 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
.code32 .code32
@ -90,7 +82,8 @@ addrsize_set_high:
post_code(0x23) post_code(0x23)
/* Set Cache-as-RAM base address. */ /* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax movl $_car_mtrr_start, %eax
orl $MTRR_TYPE_WRBACK, %eax
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
@ -98,7 +91,8 @@ addrsize_set_high:
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr rdmsr
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
post_code(0x25) post_code(0x25)
@ -122,10 +116,11 @@ addrsize_set_high:
movl %eax, %cr0 movl %eax, %cr0
/* Clear the cache memory region. This will also fill up the cache. */ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi cld
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
xorl %eax, %eax xorl %eax, %eax
movl $_car_mtrr_start, %edi
movl $_car_mtrr_size, %ecx
shr $2, %ecx
rep stosl rep stosl
post_code(0x26) post_code(0x26)
@ -142,13 +137,13 @@ addrsize_set_high:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/ */
movl $_program, %eax movl $_program, %eax
andl $(~(XIP_ROM_SIZE - 1)), %eax andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_xip_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
post_code(0x28) post_code(0x28)

23
src/cpu/intel/car/non-evict/cache_as_ram.S
View File

@ -4,10 +4,6 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE \
+ CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define NoEvictMod_MSR 0x2e0 #define NoEvictMod_MSR 0x2e0
#define BBL_CR_CTL3_MSR 0x11e #define BBL_CR_CTL3_MSR 0x11e
@ -91,7 +87,8 @@ addrsize_set_high:
post_code(0x23) post_code(0x23)
/* Set Cache-as-RAM base address. */ /* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax movl $_car_mtrr_start, %eax
orl $MTRR_TYPE_WRBACK, %eax
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
@ -99,18 +96,21 @@ addrsize_set_high:
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr rdmsr
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax movl $_rom_mtrr_base, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_rom_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
post_code(0x25) post_code(0x25)
@ -171,10 +171,11 @@ end_microcode_update:
wrmsr wrmsr
/* Clear the cache memory region. This will also fill up the cache. */ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi cld
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
xorl %eax, %eax xorl %eax, %eax
movl $_car_mtrr_start, %edi
movl $_car_mtrr_size, %ecx
shr $2, %ecx
rep stosl rep stosl
/* enable the 'no eviction run' state */ /* enable the 'no eviction run' state */

30
src/cpu/intel/car/p3/cache_as_ram.S
View File

@ -4,14 +4,6 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
.code32 .code32
@ -78,14 +70,16 @@ addrsize_set_high:
/* Set Cache-as-RAM base address. */ /* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax movl $_car_mtrr_start, %eax
orl $MTRR_TYPE_WRBACK, %eax
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr rdmsr
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
post_code(0x2b) post_code(0x2b)
@ -107,12 +101,14 @@ addrsize_set_high:
/* Read then clear the CAR region. This will also fill up the cache. /* Read then clear the CAR region. This will also fill up the cache.
* IMPORTANT: The read is mandatory. * IMPORTANT: The read is mandatory.
*/ */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
cld cld
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx movl $_car_mtrr_start, %edi
movl $_car_mtrr_size, %ecx
shr $2, %ecx
movl %ecx, %ebx
movl %edi, %esi
rep lodsl rep lodsl
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx movl %ebx, %ecx
xorl %eax, %eax xorl %eax, %eax
rep stosl rep stosl
@ -130,13 +126,13 @@ addrsize_set_high:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/ */
movl $_program, %eax movl $_program, %eax
andl $(~(XIP_ROM_SIZE - 1)), %eax andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_xip_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
post_code(0x2e) post_code(0x2e)

32
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@ -8,14 +8,6 @@
/* Macro to access Local APIC registers at default base. */ /* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
.code32 .code32
@ -219,14 +211,16 @@ sipi_complete:
/* Set Cache-as-RAM base address. */ /* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax movl $_car_mtrr_start, %eax
orl $MTRR_TYPE_WRBACK, %eax
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr rdmsr
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
post_code(0x2b) post_code(0x2b)
@ -277,12 +271,13 @@ no_msr_11e:
/* Cache the whole rom to fetch microcode updates */ /* Cache the whole rom to fetch microcode updates */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax movl $_rom_mtrr_base, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_rom_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
@ -332,13 +327,13 @@ cache_rom:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/ */
movl $_program, %eax movl $_program, %eax
andl $(~(XIP_ROM_SIZE - 1)), %eax andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $_xip_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
fill_cache: fill_cache:
@ -352,8 +347,9 @@ fill_cache:
/* Clear the cache memory region. This will also fill up the cache. */ /* Clear the cache memory region. This will also fill up the cache. */
cld cld
xorl %eax, %eax xorl %eax, %eax
movl $CACHE_AS_RAM_BASE, %edi movl $_car_mtrr_start, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx movl $_car_mtrr_size, %ecx
shr $2, %ecx
rep stosl rep stosl
/* Setup the stack. */ /* Setup the stack. */