cpu/intel/car: Use symbols for CAR MTRR setup
Change-Id: I32d7337ccf8005c7fb65d2efea40c122093d4dd9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
Nico Huber
parent
ed318f2001
commit
dc6bb6cb82
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@ -4,14 +4,6 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
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#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
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#endif
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#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
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.global bootblock_pre_c_entry
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.code32
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@ -90,7 +82,8 @@ addrsize_set_high:
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post_code(0x23)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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movl $_car_mtrr_start, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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xorl %edx, %edx
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wrmsr
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@ -98,7 +91,8 @@ addrsize_set_high:
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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rdmsr
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_car_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(0x25)
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@ -122,10 +116,11 @@ addrsize_set_high:
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movl %eax, %cr0
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/* Clear the cache memory region. This will also fill up the cache. */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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cld
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xorl %eax, %eax
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movl $_car_mtrr_start, %edi
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movl $_car_mtrr_size, %ecx
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shr $2, %ecx
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rep stosl
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post_code(0x26)
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@ -142,13 +137,13 @@ addrsize_set_high:
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(XIP_ROM_SIZE - 1)), %eax
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andl $_xip_mtrr_mask, %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_xip_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(0x28)
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@ -4,10 +4,6 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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#define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE \
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+ CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#define NoEvictMod_MSR 0x2e0
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#define BBL_CR_CTL3_MSR 0x11e
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@ -91,7 +87,8 @@ addrsize_set_high:
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post_code(0x23)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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movl $_car_mtrr_start, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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xorl %edx, %edx
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wrmsr
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@ -99,18 +96,21 @@ addrsize_set_high:
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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rdmsr
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_car_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
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movl $_rom_mtrr_base, %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_rom_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(0x25)
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@ -171,10 +171,11 @@ end_microcode_update:
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wrmsr
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/* Clear the cache memory region. This will also fill up the cache. */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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cld
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xorl %eax, %eax
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movl $_car_mtrr_start, %edi
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movl $_car_mtrr_size, %ecx
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shr $2, %ecx
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rep stosl
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/* enable the 'no eviction run' state */
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@ -4,14 +4,6 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
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#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
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#endif
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#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
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.global bootblock_pre_c_entry
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.code32
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@ -78,14 +70,16 @@ addrsize_set_high:
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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movl $_car_mtrr_start, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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xorl %edx, %edx
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wrmsr
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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rdmsr
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_car_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(0x2b)
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@ -107,12 +101,14 @@ addrsize_set_high:
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/* Read then clear the CAR region. This will also fill up the cache.
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* IMPORTANT: The read is mandatory.
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*/
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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cld
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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movl $_car_mtrr_start, %edi
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movl $_car_mtrr_size, %ecx
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shr $2, %ecx
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movl %ecx, %ebx
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movl %edi, %esi
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rep lodsl
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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movl %ebx, %ecx
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xorl %eax, %eax
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rep stosl
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@ -130,13 +126,13 @@ addrsize_set_high:
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(XIP_ROM_SIZE - 1)), %eax
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andl $_xip_mtrr_mask, %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_xip_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(0x2e)
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@ -8,14 +8,6 @@
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/* Macro to access Local APIC registers at default base. */
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#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
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#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
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#endif
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#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
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.global bootblock_pre_c_entry
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.code32
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@ -219,14 +211,16 @@ sipi_complete:
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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movl $_car_mtrr_start, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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xorl %edx, %edx
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wrmsr
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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rdmsr
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_car_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(0x2b)
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@ -277,12 +271,13 @@ no_msr_11e:
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/* Cache the whole rom to fetch microcode updates */
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
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movl $_rom_mtrr_base, %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_rom_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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@ -332,13 +327,13 @@ cache_rom:
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(XIP_ROM_SIZE - 1)), %eax
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andl $_xip_mtrr_mask, %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $_xip_mtrr_mask, %eax
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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fill_cache:
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@ -352,8 +347,9 @@ fill_cache:
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/* Clear the cache memory region. This will also fill up the cache. */
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cld
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xorl %eax, %eax
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movl $CACHE_AS_RAM_BASE, %edi
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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movl $_car_mtrr_start, %edi
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movl $_car_mtrr_size, %ecx
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shr $2, %ecx
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rep stosl
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/* Setup the stack. */
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