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nb/intel/nehalem: Use the common mrc cache driver 

The common mrc cache driver allows to save the raminit training
results to a separate fmap region which is more manageable than a
cbfsfile.

Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans 2018-01-29 10:14:48 +01:00 committed by Patrick Georgi
parent 0e9bbcc905
commit dc71e25494
3 changed files with 10 additions and 17 deletions
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2
src/northbridge/intel/nehalem/Kconfig
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@ -21,7 +21,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select RELOCATABLE_RAMSTAGE select RELOCATABLE_RAMSTAGE
select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CACHE_MRC_SETTINGS
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT

10
src/northbridge/intel/nehalem/Makefile.inc
View File

@ -29,14 +29,4 @@ romstage-y += ../../../arch/x86/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
$(obj)/mrc.cache:
dd if=/dev/zero count=1 \
bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
tr '\000' '\377' > $@
cbfs-files-y += mrc.cache
mrc.cache-file := $(obj)/mrc.cache
mrc.cache-align := 0x10000
mrc.cache-type := mrc_cache
endif endif

15
src/northbridge/intel/nehalem/raminit.c
View File

@ -43,7 +43,7 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/intel/speedstep.h> #include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <northbridge/intel/common/mrc_cache.h> #include <mrc_cache.h>
#endif #endif
#if !REAL #if !REAL
@ -91,6 +91,8 @@ typedef struct {
u8 largest; u8 largest;
} timing_bounds_t[2][2][2][9]; } timing_bounds_t[2][2][2][9];
#define MRC_CACHE_VERSION 1
struct ram_training { struct ram_training {
/* [TM][CHANNEL][SLOT][RANK][LANE] */ /* [TM][CHANNEL][SLOT][RANK][LANE] */
u16 lane_timings[4][2][2][2][9]; u16 lane_timings[4][2][2][2][9];
@ -1741,17 +1743,18 @@ static void save_timings(struct raminfo *info)
printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8);
/* Save the MRC S3 restore data to cbmem */ /* Save the MRC S3 restore data to cbmem */
store_current_mrc_cache(&train, sizeof(train)); mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
&train, sizeof(train));
} }
#if REAL #if REAL
static const struct ram_training *get_cached_training(void) static const struct ram_training *get_cached_training(void)
{ {
struct mrc_data_container *cont; struct region_device rdev;
cont = find_current_mrc_cache(); if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
if (!cont) &rdev))
return 0; return 0;
return (void *)cont->mrc_data; return (void *)rdev_mmap_full(&rdev);
} }
#endif #endif