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soc/intel/tigerlake: Skip GPIO configuration from FSP 

FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.

BUG=b:166790597, b:146390704
BRANCH=none
TEST=build and boot volteer proto2

Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-08-28 13:22:30 -07:00 committed by Patrick Georgi
parent 6727276a65
commit dc87025ce4
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/tigerlake/romstage/fsp_params.c
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@ -87,6 +87,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
m_cfg->PchIshEnable = is_dev_enabled(dev);
/* Skip GPIO configuration from FSP */
m_cfg->GpioOverride = 0x1;
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;