From dc873cc0c6402f289f34090f0fdb34588a04a9c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 21 Nov 2020 17:59:41 +0200 Subject: [PATCH] arch/x86: Clean up bootblock assembly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have identical gdtptr16 and gdtptr. The reference in gdtptr_offset calculation is not accounted for when considering --gc-sections, so to support linking gdt_init.S separately add dummy use of gdtptr symbol. Realmode execution already accessed gdt that was located outside [_start16bit,_estart16bit] region. Remove latter symbol as the former was not really a start of region, but entry point symbol. With the romcc bootblock solution, entry32.inc may have been linked into romstage before, but the !ENV_BOOTBLOCK case seems obsolete now. Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/arch/x86/bootblock.ld | 2 +- src/cpu/x86/16bit/entry16.inc | 13 +++--------- src/cpu/x86/32bit/entry32.inc | 20 +------------------ .../common/block/cpu/noncar/memlayout_x86.ld | 2 +- 4 files changed, 6 insertions(+), 31 deletions(-) diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 12f932c2dc..849addd2e2 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -gdtptr16_offset = gdtptr16 & 0xffff; +gdtptr_offset = gdtptr & 0xffff; nullidt_offset = nullidt & 0xffff; /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 13d12beb66..2665cc69ae 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -108,7 +108,7 @@ _start16bit: movw $nullidt_offset, %bx subw %ax, %bx lidt %cs:(%bx) - movw $gdtptr16_offset, %bx + movw $gdtptr_offset, %bx subw %ax, %bx lgdtl %cs:(%bx) @@ -127,11 +127,8 @@ _start16bit: * The gdt is defined in entry32.inc, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ -.align 4 -.globl gdtptr16 -gdtptr16: - .word gdt_end - gdt -1 /* compute the table limit */ - .long gdt /* we know the offset */ +__gdtptr: + .long gdtptr .align 4 .globl nullidt @@ -139,7 +136,3 @@ nullidt: .word 0 /* limit */ .long 0 .word 0 - -.globl _estart16bit -_estart16bit: - .code32 diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index be67b534cb..85094483e5 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -8,29 +8,11 @@ .code32 /* - * When we come here we are in protected mode. We expand - * the stack and copies the data segment from ROM to the - * memory. - * - * After that, we call the chipset bootstrap routine that - * does what is left of the chipset initialization. - * + * When we come here we are in protected mode. * NOTE aligned to 4 so that we are sure that the prefetch * cache will be reloaded. - * - * In the bootblock there is already a ljmp to __protected_start and - * the reset vector jumps to symbol _start16bit in entry16.inc from - * the reset vectors's symbol which is _start. Therefore, don't - * expose the _start symbol for bootblock. */ .align 4 -#if !ENV_BOOTBLOCK -.globl _start -_start: -#endif - - lgdt %cs:gdtptr - ljmp $ROM_CODE_SEG, $__protected_start __protected_start: /* Save the BIST value */ diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index f702b4b201..352472e18b 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -102,7 +102,7 @@ SECTIONS #if ENV_BOOTBLOCK -gdtptr16_offset = gdtptr16 & 0xffff; +gdtptr_offset = gdtptr & 0xffff; nullidt_offset = nullidt & 0xffff; SECTIONS {